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Advances in Condensed Matter Physics
Volume 2015, Article ID 423791, 6 pages
Research Article

Analysis of Low Dimensional Nanoscaled Inversion-Mode InGaAs MOSFETs for Next-Generation Electrical and Photonic Applications

1Jiangsu Key Laboratory of ASIC Design, Nantong University, Nantong 226019, China
2Laboratory of Advanced Material, Fudan University, Shanghai 200438, China

Received 21 October 2014; Accepted 17 December 2014

Academic Editor: Wen Lei

Copyright © 2015 C. H. Yu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


The electrical characteristics of In0.53Ga0.47As MOSFET grown with Si interface passivation layer (IPL) and high gate oxide HfO2 layer have been investigated in detail. The influences of Si IPL thickness, gate oxide HfO2 thickness, the doping depth, and concentration of source and drain layer on output and transfer characteristics of the MOSFET at fixed gate or drain voltages have been individually simulated and analyzed. The determination of the above parameters is suggested based on their effect on maximum drain current, leakage current, saturated voltage, and so forth. It is found that the channel length decreases with the increase of the maximum drain current and leakage current simultaneously. Short channel effects start to appear when the channel length is less than 0.9 μm and experience sudden sharp increases which make device performance degrade and reach their operating limits when the channel length is further lessened down to 0.5 μm. The results demonstrate the usefulness of short channel simulations for designs and optimization of next-generation electrical and photonic devices.