High-Electron-Mobility SiGe on Sapphire Substrate for Fast Chipsets

Table 2

Comparison of Si, SOI, and SiGe on Si and LM-SGOI technologies.

Technology	Si	SOI/SGOI	SiGe on Si	SiGe on sapphire (NASA LaRC)
Fabrication	Single crystal ingot	Hydrogen crack	Gradient layer, super lattice	Lattice-matched growth
Growth method	Czochralski	Wafer bonding	Epitaxial growth	Epitaxial growth
Lattice-matched Ge content	0%	0%	0%	85% with sapphire substrate
Ge content in strained layer before defects	0%	Usually 0~8%	Usually 0~8%	85% achieved
Ge content in relaxed layer	0% (not available)	Up to 25% with severe defects	Up to 25% with severe defects	85% achieved with 0.2% defects
Parasitic capacitance reduction	No	Yes	No	Yes
Device	Bipolar junction transistor (BJT), CMOS	BJT, CMOS/heterojunction bipolar transistor (HBT), CMOS	HBT	HBT, CMOS
Improvement	Conventional technology	High speed with insulating substrate	High speed (ultrathin SiGe lower collector voltage of HBT)	High speed with thick and thin SiGe layer with insulating substrate, higher device yield with lower defects