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Advances in Condensed Matter Physics
Volume 2018, Article ID 2683723, 5 pages
https://doi.org/10.1155/2018/2683723
Research Article

Digital Simulation of Superconductive Memory System Based on Hardware Description Language Modeling

Department of Electronics & Communication Engineering, SRM Institute of Science and Technology, Chennai, India

Correspondence should be addressed to S. Narendran; moc.liamtoh@rahdirs.neran

Received 11 February 2018; Accepted 24 April 2018; Published 27 May 2018

Academic Editor: Sergei Sergeenkov

Copyright © 2018 S. Narendran and J. Selvakumar. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

We have modeled a memory system using Josephson Junction to attain low power consumption using low input voltage compared to conventional Complementary Metal Oxide Semiconductor-Static Random Access Memory (CMOS-SRAM). We attained the low power by connecting a shared/common bit line and using a 1-bit memory cell. Through our design we may attain 2.5–3.5 microwatts of power using lower input voltage of 0.6 millivolts. Comparative study has been made to find which memory system will attain low power consumption. Conventional SRAM techniques consume power in the range of milliwatts with the supply input in the range of 0-10 volts. Using HDL language, we made a memory logic design of RAM cells using Josephson Junction in FreeHDL software which is dedicated only for Josephson Junction based design. With use of XILINX, we have calculated the power consumption and equivalent Register Transfer Level (RTL) schematic is drawn.

1. Introduction

For low power consumption and high performance computing, Single flux Quantum (SFQ) is widely used, which is an alternate principle for Complementary Metal Oxide Semiconductor (CMOS) technology. Many SFQ techniques are devolved to attain high speed and low power consumption. Various approaches have been developed on Josephson, CMOS hybrid memory cell, which is high density CMOS memory array and low power Single flux Quantum (SFQ) logic [14]. In addition, the hybrid model must work at cryogenic temperature. The 64kb hybrid static CMOS RAM has been discussed in [5]; the estimated power consumption of this hybrid logic is 20 mW for read and 53.7 mW for write operation. In [6], further reduction on power consumption is achieved by introducing a binary tree decoder and with help of data driver, they attain 54% and 8% of write and read operation. We attain large scale high speed memory using cryogenic experience to match the ultra-speed processor in the same cryogenic temperature. Many developments and demonstrations of hybrid memory logic have been evolved using SFQ and RSFQ (Rapid Single Flux Quantum) logic.

In this paper, we developed a RAM using Reciprocal Quantum Logic at cryogenic temperature. The proposed memory system is of static nature which is composed of decoder and sense amplification circuit. In Section 2, we have discussed convention SRAM using 6T and 8T transistor. We have designed a RAM using RQL which is discussed in Section 3. Comparative study and results are discussed in Section 4 and we have concluded our remarks in Section 5.

2. Conventional CMOS Memory Cell Design

The most commonly used control signals in CMOS RAM cell are Write Enable (WE), Output Enable (OE), and Chip Select (CS). Conventional 6T CMOS memory cell consists of four NMOS and two PMOS counts with separate bit line and word line. The average power consumption of 6T SRAM cell is 46mW and area required is 5μm2. For 8T transistor, the dynamic power consumption will be 0.035μW. For both SRAM memory cell, the voltage at both bit lines is precharged before the read operation starts. Consider logic 0 at transistor M3 and logic 1 at M4; the particular memory can be selected using word line and bit line correspondingly according to discharge of current flows from the supply voltage. For write operation, the bit line (BL) will complement its signal from logic 0 to logic 1 and vice versa. The cross coupled inverter structure will generate high gain to interchange the voltages passing through the transistor.

By use of NMOS and PMOS logic, corresponding 6T and 8T SRAM cells are formed in Figures 1 and 2. For 6T SRAM cell, there are four NMOS and two PMOS are used. And, for 8T SRAM CMOS cell it requires six NMOS and two PMOS logic structures. Furthermore, different SRAM architectures have been developed using 7T and 9T CMOS cells.

Figure 1: Conventional 6T CMOS-SRAM cell [7].
Figure 2: Conventional 8T SRAM CMOS cell.

3. Superconductive Memory Cell

In SRAM cell design, they are incorporable in terms of power dissipation due to high capacitance buses. Due to excessive access of capacitance buses, low-voltage low power cell designs are developed in CMOS families. With the help of shared bit line cell configuration of SRAM cell libraries, we can achieve ultra-low power dissipation. MUX based charged sense amplifiers are used for read operation. For write operation, a bit line precharged technique is used to attain high speed write operation [8].

With the help of low-voltage low power (LVLP) technique, the normalized form of RAM cell design is made by replacing MOS technology with Josephson Junction (JJ) technology. Below, Figure 3 shows the structure of RAM architecture by replacing CMOS cell libraries with Reciprocal Quantum Logic structure.

Figure 3: Structure of a memory system.

Reciprocal Quantum Logic (RQL) is one of the high speed low power consumption superconductive logics. RQL circuits are designed using alternating current phenomena rather all CMOS or any digital circuits designed using direct current as input. In [911], RQL circuits are designed using the basic gates of RQL as ANDOR, ANOTB, Latch circuit, and XOR logic gates. In our design we also used the basic gates to form RAM logic to consume less power comparative to the older techniques. Other superconducting logics include RSFQ, AQFP, and eSFQ, which are successor of convention CMOS logic design. Those logics have their own pros and cons. By using RSFQ [1214], many articles have been published for the design of RAM and processors which can work 25% to 35% more in performance comparative to the CMOS RAM cells.

4. Simulation Results of RQL Based RAM

With the help of Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL), the coding of RAM cell is designed and corresponding results are found out. By using XILINX software and FreeHDL software, we have generated the RTL schematic view of our RAM design. Figure 4 shows the Register Transfer Level (RTL) schematic view of RAM cell using RQL.

Figure 4: RTL schematic view of RAM using Reciprocal Quantum Logic.

We have compared our result with previously developed RAM cell like 6T, 8T, Hybrid Josephson Junction- (JJ-) CMOS for 64Kb, and hybrid binary decoder of JJ-CMOS. We have presented it in Table 1. For the results obtained in Table 1, we made a chart comparison and it is shown in Figure 5.

Table 1: Comparison of power consumption.
Figure 5: Power comparison of various technologies.

5. Conclusion

We have designed a RAM cell using RQL superconducting logic. We achieved the power consumption of 2.6μW for read operation and 3.45μW for write operation, which is very much less compared to other technologies. We designed the RAM using HDL language and analysed the power using XILINX software. Since we have used the Reciprocal Quantum Logic (RQL), we can further implement this technique in real time application for high speed processor to support high speed applications. Our future work will be designing a processor based on RQL and implementing this RAM technique to that processor.

Data Availability

The data used to support the findings of this study are available from the corresponding author upon request.

Conflicts of Interest

The authors declare that there are no conflicts of interest regarding the publication of this paper

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