Novel Basic Block of Multilevel Inverter Using Reduced Number of On-State Switches and Cascaded Circuit Topology

Table 1

Switching sequence and output voltages of proposed topology.

Sw. mode									Output voltage
1	1	0	0	1	0	1	0	0
2	1	0	1	0	0	1	0	0
2′	1	0	0	1	1	0	0	0
3	1	0	1	0	1	0	0	0
4	0	1	0	1	0	1	0	0
4′	1	0	0	0	0	1	1	0
5	0	1	1	0	0	1	0	0	0
5′	0	1	0	1	1	0	0	0
6	0	1	1	0	1	0	0	0
6′	1	0	0	0	1	0	0	1
7	0	1	0	0	0	1	1	0
8	0	1	0	0	1	0	1	0
8′	0	1	0	0	0	1	0	1
9	0	1	0	0	1	0	0	1