Advances in Electrical Engineering

Volume 2017, Article ID 5640926, 16 pages

https://doi.org/10.1155/2017/5640926

## Novel Basic Block of Multilevel Inverter Using Reduced Number of On-State Switches and Cascaded Circuit Topology

^{1}Department of Electrical Engineering, G. H. Raisoni College of Engineering, CRPF Gate No. 3, Hingna Road, Digdoh Hills, Nagpur, Maharashtra 440016, India^{2}Department of Electrical Engineering, Shri Ramdeobaba College of Engineering & Management, Ramdeo Tekdi, Gittikhadan, Katol Road, Nagpur 440013, India

Correspondence should be addressed to Sanjay Bodkhe; ude.cenkr@bsehkdob

Received 22 November 2016; Revised 7 March 2017; Accepted 21 March 2017; Published 18 April 2017

Academic Editor: George E. Tsekouras

Copyright © 2017 Aparna Prayag and Sanjay Bodkhe. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

In this paper a basic block of novel topology of multilevel inverter is proposed. The proposed approach significantly requires reduced number of dc voltage sources and power switches to attain maximum number of output voltage levels. By connecting basic blocks in series a cascaded multilevel topology is developed. Each block itself is also a multilevel inverter. Analysis of proposed topology is carried out in symmetric as well as asymmetric operating modes. The topology is investigated through computer simulation using MATLAB/Simulink and validated experimentally on prototype in the laboratory.

#### 1. Introduction

Recently, multilevel inverter technology has become popular in industry for medium and high voltage applications. Hi-Tech industry demands quality electric power that multilevel inverter technology can supply. Multilevel inverter uses number of power semiconductor devices, dc sources (batteries/capacitors) to synthesize staircase output voltage waveform. By increasing number of levels the output voltage waveform approaches near to sine wave improving its quality. As compared to traditional two-level inverter it generates high quality output voltage using low switching frequency with low harmonic distortion. Other advantages of this technology are lower switching losses, have more efficiency, have low voltage stress on power switches, have low electromagnetic interference, and have low* dv/dt* stress on load. Due to these advantages they found wide applications in adjustable speed drives, HVDC, FACTS, wind farms, photovoltaic systems, electric vehicles, and so on [1–3].

The popular commercially available topologies of multilevel inverter are neutral point clamped (NPC) proposed by Nabae et al. [4], flying capacitor (FC) proposed by Meynard and Foch [5], and cascaded H bridge (CHB) proposed by Peng and Lai [6]. NPC is also known as diode clamped (DC) multilevel inverter which is well-known as first generation of multilevel technology. It was basically a three-level inverter and known as state-of-the-art of multilevel technology. The FC topology is an alternative to NPC topology which uses capacitors in ladder form to clamp voltage instead of diodes. To generate higher levels both topologies, NPC and FC, require many components and also suffer due to capacitor voltage imbalance problem [7]. In CHB, H-bridges with separate dc sources of equal magnitude are connected in series. This characteristic makes the topology modular. Total output voltage is obtained by adding voltages generated by each H-bridge. Each H-bridge generates three voltage levels. This is an appropriate topology to generate large number of levels as it requires less number of components.

Recently, some new multilevel inverter topologies have been presented. It includes asymmetric and/or hybrid inverters [8]. In asymmetric topology unequal dc source magnitudes are used while hybrid inverters are designed by using different topologies, applying different modulation techniques or semiconductor technologies.

Nowadays, research is engaged to develop novel topologies with objectives to reduce number of components, dc sources, and complexity of the circuit [9–12]. Total harmonic distortion for output voltage waveform, power losses, and voltage stress on power switches are also optimization factors while designing novel topologies [13]. Some of the recently proposed multilevel inverter topologies with reduced power switch count are reviewed and analysed in [14].

##### 1.1. Related Work

In order to increase the number of output voltage levels, various new cascaded topologies are presented. In [15], a new basic unit for a cascaded multilevel inverter is proposed. By the series connection of several basic units, a cascaded multilevel inverter can generate positive levels at the output. In order to generate all voltage levels an H-bridge is added to the proposed inverter. Four different algorithms are proposed to determine the magnitude of the dc voltage sources, to generate even and odd voltage levels at the output.

In [16], a novel 17-level inverter configuration is presented. This configuration is formed by cascading a three-level flying capacitor and three floating capacitor H-bridges. It uses single dc power supply. It can control capacitor voltage during inverter switching cycles.

A new type of cascaded modular multilevel inverters (CMMLIs) is presented in [17]. It can produce a considerable number of output voltage levels with a reasonable number of components. Two same basic units are connected in each series stage of the proposed CMMLI. To determine an appropriate value for the dc sources’ magnitude four different algorithms are also presented in this paper.

A new module named Envelope Type (E-Type) module for cascaded multilevel inverter is proposed in [18]. It can generate 13 levels with reduced components. In [19], a new general multilevel inverter topology based on cascade connection of submultilevel units is presented. This topology uses reduced switching components, dc voltage sources, and blocked voltage by switches. The topology can be used in high voltage applications as it uses the switches with low voltage rating. In [20], single phase *π*-type five-level inverter using three-terminal switch-network is proposed. For multilevel power inversion this new structure is suitable with low dc-bus voltage. Using only four active power switches five-level operation can be attained.

A new cascaded seven-level inverter is developed in [21]. It uses single dc source and switched capacitor technique. The proposed topology substitutes all the separate dc voltage sources with capacitors, as compared with the conventional cascaded multilevel inverter. In [22], a new topology of six-level inverter is proposed. It consists of flying capacitor inverter units inside and two-level inverter units outside. It is suitable for medium-voltage high power applications. A new symmetric cascade multilevel inverters structure is presented in [23]. This structure requires minimum number of power electronic components, gate driver circuits, a power diode, and a dc voltage source. In [24], a new method for generating higher number of output voltage levels by stacking multilevel converters with lower voltage space vector structures is presented. Low voltage devices are used in stacked structure. It can be used in electric vehicles as direct battery drive is possible. A new fundamental switch-ladder multilevel inverter structure and cascade switch-ladder multilevel inverter topology are presented in [25]. To generate maximum number of levels with minimum number of switching elements, dc sources, and voltage on switches, the proposed cascade topology is optimized.

In this paper, a basic unit of new multilevel inverter topology is suggested. This single unit can generate different output voltage levels. Also in order to generate higher levels a cascaded topology with series connection of basic blocks is proposed. The detailed working of proposed topology is presented. Also, analysis is carried out in both symmetric and asymmetric operating modes. The proposed structure uses minimum number of on-state switches and dc sources as compared to topologies presented in literature.

The rest of the paper is organized as follows. Section 2 presents basic block of proposed topology. Detailed operation of proposed topology is described in this section. In Section 3 a generalized cascaded circuit topology and seven different combinations to select magnitude of dc voltage sources for this circuit are addressed. Section 4 contains calculation of standing voltage of switches. Section 5 presents the comparison among seven different combinations as well as with conventional topologies of CHB. Simulation and experimental results for laboratory prototype are given in Section 6. Finally conclusions are summarized in Section 7.

#### 2. Proposed Topology

The basic block of proposed multilevel inverter topology is shown in Figure 1. It consists of eight power semiconductor switches (, and ) and two dc voltage sources ( and ). When voltage sources are of equal magnitude (), the basic block operates in symmetric mode and generates five levels at output (two positive, two negative, and zero). However in order to generate more output levels unequal magnitudes of voltage sources can be selected and the basic block operates in asymmetric mode.(i)Case I: ; it can generate seven levels at output (three positive, three negative, and zero).(ii)Case II: ; it can generate nine levels at output (four positive, four negative, and zero).