Table of Contents
Advances in Electronics
Volume 2014, Article ID 365689, 21 pages
Review Article

FinFETs: From Devices to Architectures

Department of Electrical Engineering, Princeton University, Princeton, NJ 08544, USA

Received 4 June 2014; Accepted 23 July 2014; Published 7 September 2014

Academic Editor: Jaber Abu Qahouq

Copyright © 2014 Debajit Bhattacharya and Niraj K. Jha. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Since Moore’s law driven scaling of planar MOSFETs faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to the presence of multiple (two/three) gates, FinFETs/Trigate FETs are able to tackle short-channel effects (SCEs) better than conventional planar MOSFETs at deeply scaled technology nodes and thus enable continued transistor scaling. In this paper, we review research on FinFETs from the bottommost device level to the topmost architecture level. We survey different types of FinFETs, various possible FinFET asymmetries and their impact, and novel logic-level and architecture-level tradeoffs offered by FinFETs. We also review analysis and optimization tools that are available for characterizing FinFET devices, circuits, and architectures.