Table of Contents
Advances in Electronics
Volume 2014, Article ID 564613, 6 pages
Research Article

Design of Low Power and Efficient Carry Select Adder Using 3-T XOR Gate

ECE Department, Shaheed Bhagat Singh State Technical Campus, Ferozepur, Punjab 152004, India

Received 16 June 2014; Accepted 7 September 2014; Published 22 September 2014

Academic Editor: Liwen Sang

Copyright © 2014 Gagandeep Singh and Chakshu Goel. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In digital systems, mostly adder lies in the critical path that affects the overall performance of the system. To perform fast addition operation at low cost, carry select adder (CSLA) is the most suitable among conventional adder structures. In this paper, a 3-T XOR gate is used to design an 8-bit CSLA as XOR gates are the essential blocks in designing higher bit adders. The proposed CSLA has reduced transistor count and has lesser power consumption as well as power-delay product (PDP) as compared to regular CSLA and modified CSLA.