Reconfigurable CPLAG and Modified PFAL Adiabatic  Logic Circuits

<div>Avg. input power required for <svg height="12.4257pt" id="M25" style="vertical-align:-3.427751pt" version="1.1" viewbox="-0.0498162 -8.99795 12.8178 12.4257" width="12.8178pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.0135,0,0,-0.0135,0,0)"><path d="M697 650H468L461 623L492 619C539 613 547 605 518 546C481 471 367 264 278 116H276C239 278 197 500 186 567C180 604 185 613 226 619L252 623L260 650H24L17 623C78 617 92 613 108 533L216 -11H247C365 200 515 462 560 529C616 612 624 615 689 623L697 650Z" id="g113-87"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="709" vert-adv-y="709"></glyph.data></g><g transform="matrix(.0095,0,0,-0.0095,7.641,3.264)"><path d="M460 334C460 396 434 451 378 451C330 451 241 408 148 300H146L237 679C241 697 241 710 232 710C213 710 153 684 67 675L66 646H95C141 646 145 642 134 595L39 170C23 97 31 54 46 33C64 8 100 -12 137 -12C178 -12 234 3 298 43C391 101 460 222 460 334ZM371 320C371 204 316 89 248 51C230 41 208 37 192 37C143 37 102 72 119 166C124 194 129 215 135 235C202 323 298 392 335 392C353 392 371 372 371 320Z" id="g50-99"></path><glyph.data ascent="3443" descent="-2856" horiz-adv-x="478" vert-adv-y="478"></glyph.data></g></svg> for DFF @RCPLAG Nand.</div>

Advances in Electronics

Reconfigurable CPLAG and Modified PFAL Adiabatic Logic Circuits

Figure 13