Table of Contents
Advances in Electronics
Volume 2015, Article ID 202131, 10 pages
http://dx.doi.org/10.1155/2015/202131
Research Article

Reconfigurable CPLAG and Modified PFAL Adiabatic Logic Circuits

1Department of ECE, Mewar University, Rajasthan 312901, India
2Department of ECE, BVCOE, Paschim Vihar, New Delhi 110063, India
3SoE, CDAC Noida, Ministry of Communications and IT, Government of India, Noida, Uttar Pradesh 201307, India

Received 30 September 2014; Revised 25 December 2014; Accepted 25 December 2014

Academic Editor: Meiyong Liao

Copyright © 2015 Manoj Sharma and Arti Noor. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. R. Landauer, “Irreversibility and heat generation in the computing process,” IBM Journal of Research and Development, vol. 5, no. 3, pp. 183–191, 1961. View at Publisher · View at Google Scholar · View at MathSciNet
  2. A. Vetuli, S. D. Pascoli, and L. M. Reyneri, “Positive feedback in adiabatic logic,” Electronics Letters, vol. 32, no. 20, pp. 1867–1869, 1996. View at Publisher · View at Google Scholar · View at Scopus
  3. A. Blotti and R. Saletti, “Ultralow-power adiabatic circuit semi-custom design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 11, pp. 1248–1253, 2004. View at Publisher · View at Google Scholar · View at Scopus
  4. M. P. Frank, “Common mistakes in adiabatic logic design and how to avoid them,” in Proceedings of the International Conference on Embedded Systems and Applications (ESA'03), pp. 216–222, Las Vegas, Nev, USA, June 2003. View at Scopus
  5. M. P. Frank, Realistic Cost-Efficiency Advantages for Reversible Computing in Coming Decades, UF Reversible Computing Project Memo #M16, 2002, http://www.cise.ufl.edu/research/revcomp/writing.html.
  6. V. S. Kanchana Bhaaskaran, “Asymmetrical positive feedback adiabatic logic for low power and higher frequency,” in Proceedings of the International Conference on Advances in Recent Technologies in Communication and Computing, pp. 5–9, October 2010.
  7. M. Kumari, M. L. Keote, and N. Aman, “Low power adiabatic complementary pass transistor logic for sequential circuit,” International Journal of Research in Computer and Communication Technology, vol. 3, no. 1, 2014. View at Google Scholar
  8. C. P. Kumar, S. K. Tripathy, and R. Tripathi, “High performance sequential circuits with adiabatic complementary pass-transistor logic (ACPL),” in Proceedings of the IEEE Region 10 Conference (TENCON '09), pp. 1–4, November 2009. View at Publisher · View at Google Scholar · View at Scopus
  9. M. Sharma and A. Noor, “Modified CPL adiabatic gated logic—MCPLAG based DPET DFF with XOR,” International Journal of Computer Applications, vol. 89, no. 19, pp. 35–41, 2014. View at Publisher · View at Google Scholar
  10. M. Sharma and A. Noor, “CPL-adiabatic gated logic (CPLAG) XOR gate,” in Proceedings of the International Conference on Advances in Computing, Communications and Informatics (ICACCI '13), pp. 575–579, August 2013. View at Publisher · View at Google Scholar · View at Scopus
  11. M. Sharma and A. Noor, “Positive feed back adiabatic logic: PFAL single edge triggered semi-adiabatic D flip flop,” African Journal of Basic & Applied Sciences, vol. 5, no. 1, pp. 42–46, 2013. View at Google Scholar
  12. M. Sharma and A. Noor, “Reconfigurable CPL adiabatic gated logic-RCPLAG based universal NAND/NOR gate,” International Journal of Computer Application, vol. 95, no. 26, pp. 27–32, 2015. View at Publisher · View at Google Scholar
  13. N. H. E. Weste and D. M. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, chapter 6, section 6.2.5.2, Pearson Education, 2006.
  14. S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits Analysis and Design, chapter 7, Tata McGraw Hill Education Private, 3rd edition, 2003.
  15. J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, chapter 3, Prentice Hall, 2nd edition, 2003.