FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

<table class="figure-group"><tr class="fig-image" id="a"><td><object data="https://static.hindawi.com/articles/aelc/volume-2015/713843/figures/713843.fig.004a.svgz" name="713843.fig.004a" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(a) </b>8-bit hybrid CSLA with a conventional CLA in the least significant stage</td></tr><tr class="fig-image" id="b"><td><object data="https://static.hindawi.com/articles/aelc/volume-2015/713843/figures/713843.fig.004b.svgz" name="713843.fig.004b" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(b) </b>8-bit hybrid CSLA featuring BEC with a least significant CLA stage</td></tr></table>

<div>Hybrid CSLAs without/with BEC logic comprising a CLA: (a) CSLA-CLA type and (b) CSLA_BEC-CLA type.</div>

Advances in Electronics

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Figure 4

Figure 4: FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders 