FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

Table 1

Maximum propagation delay and area (# BELs) of 32-bit homogeneous and heterogeneous CSLAs corresponding to diverse input partitions.

Input partition	Type of CSLA architecture	Critical path delay (ns)	Area (# BELs)
Not applicable	RCA	30.604	63
Not applicable	CSLA_CBL	37.604	63
4-4-4-4-; 4-4-4-4	CSLA	30.388	105
	CSLA_BEC	22.820	106
	CSLA-CLA	30.398	106
	CSLA_BEC-CLA	22.781	106
	CSLA-SCBCLA	29.359	108
	CSLA_BEC-SCBCLA	22.864	108
8-8-8-8	CSLA	20.280	117
	CSLA_BEC	19.176	104
	CSLA-CLA	19.260	121
	CSLA_BEC-CLA	19.059	104
	CSLA-SCBCLA	17.897	123
	CSLA_BEC-SCBCLA	18.052	110
16-16	CSLA	23.722	105
	CSLA_BEC	22.986	91
	CSLA-CLA	21.384	114
	CSLA_BEC-CLA	22.835	91
	CSLA-SCBCLA	21.097	119
	CSLA_BEC-SCBCLA	22.255	106
3-7-6-5-; 4-3-2-2	CSLA	23.337	110
	CSLA_BEC	22.411	108
	CSLA-CLA	23.337	110
	CSLA_BEC-CLA	22.411	108
	CSLA-SCBCLA	23.408	110
	CSLA_BEC-SCBCLA	22.482	108
8-7-6-4-; 3-2-2	CSLA	20.218	118
	CSLA_BEC	20.743	111
	CSLA-CLA	20.218	118
	CSLA_BEC-CLA	20.473	111
	CSLA-SCBCLA	21.403	117
	CSLA_BEC-SCBCLA	20.544	111