FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

Table 2

Maximum propagation delay and area (# BELs) of 64-bit homogeneous and heterogeneous CSLAs corresponding to different input partitions.

Input partition	Type of CSLA architecture	Critical path delay (ns)	Area (# BELs)
Not applicable	RCA	71.555	127
Not applicable	CSLA_CBL	70.525	129
4-4-4-4-; 4-4-4-4-; 4-4-4-4-; 4-4-4-4	CSLA	56.091	217
	CSLA_BEC	40.870	209
	CSLA-CLA	56.101	218
	CSLA_BEC-CLA	34.799	215
	CSLA-SCBCLA	55.062	220
	CSLA_BEC-SCBCLA	34.882	217
8-8-8-8-; 8-8-8-8	CSLA	31.866	251
	CSLA_BEC	29.119	224
	CSLA-CLA	30.846	255
	CSLA_BEC-CLA	29.002	224
	CSLA-SCBCLA	29.483	257
	CSLA_BEC-SCBCLA	27.995	230
16-16-16-16	CSLA	29.625	252
	CSLA_BEC	28.259	212
	CSLA-CLA	27.759	261
	CSLA_BEC-CLA	28.029	213
	CSLA-SCBCLA	27.427	266
	CSLA_BEC-SCBCLA	27.322	227
32-32	CSLA	40.705	217
	CSLA_BEC	40.742	189
	CSLA-CLA	38.591	215
	CSLA_BEC-CLA	40.157	189
	CSLA-SCBCLA	38.591	247
	CSLA_BEC-SCBCLA	39.682	219
8-10-9-8-7-6-; 5-4-3-2-2	CSLA	32.983	251
	CSLA_BEC	31.204	226
	CSLA-CLA	32.983	251
	CSLA_BEC-CLA	31.204	226
	CSLA-SCBCLA	33.054	251
	CSLA_BEC-SCBCLA	31.276	226