FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

Table 3

Critical path delay and area figures for CSA-based multioperand addition of four 32-bit operands, with RCA/homogeneous/heterogeneous CSLAs used in the final adder stage.

Input partition	Type of adder architecture	Critical path delay (ns)	Area (# BELs)
Not applicable	RCA	39.842	190
Not applicable	CSLA_CBL	39.842	190
8-8-8-8	CSLA	27.383	229
	CSLA_BEC	22.455	229
	CSLA-CLA	25.053	229
	CSLA_BEC-CLA	21.326	232
	CSLA-SCBCLA	23.378	227
	CSLA_BEC-SCBCLA	21.684	233