FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

Table 4

Critical path delay and area for CSA-based multioperand addition of four 64-bit operands, with RCA/homogeneous/heterogeneous CSLAs used in the final adder stage.

Input partition	Type of adder architecture	Critical path delay (ns)	Area (# BELs)
Not applicable	RCA	73.792	382
Not applicable	CSLA_CBL	71.667	383
16-16-16-16	CSLA	37.034	472
	CSLA_BEC	31.307	462
	CSLA-CLA	33.363	476
	CSLA_BEC-CLA	30.428	471
	CSLA-SCBCLA	32.008	473
	CSLA_BEC-SCBCLA	30.732	470