FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

Table 5

Critical path delay and area metrics for bit-partitioned multioperand addition of four 32-bit operands, with RCA and various homogeneous/hybrid CSLA architectures used.

Input partition	Type of adder architecture	Critical path delay (ns)	Area (# BELs)
Not applicable	RCA	39.928	190
Not applicable	CSLA_CBL	42.241	195
8-8-8-8	CSLA	32.303	458
	CSLA_BEC	29.278	311
	CSLA-CLA	31.727	359
	CSLA_BEC-CLA	28.207	325
	CSLA-SCBCLA	27.628	365
	CSLA_BEC-SCBCLA	27.056	328