FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

Table 6

Critical path delay and area parameters for bit-partitioned multioperand addition of four 64-bit operands, with RCA and various homogeneous/hybrid CSLA architectures used.

Input partition	Type of adder architecture	Critical path delay (ns)	Area (# BELs)
Not applicable	RCA	73.840	382
Not applicable	CSLA_CBL	77.946	388
16-16-16-16	CSLA	50.957	748
	CSLA_BEC	46.559	637
	CSLA-CLA	50.426	781
	CSLA_BEC-CLA	45.679	648
	CSLA-SCBCLA	45.608	800
	CSLA_BEC-SCBCLA	45.665	691