One Clock-Cycle Response 0.5 𝜇m CMOS Dual-Mode ΣΔ DC-DC Bypass Boost Converter Stable over Wide 𝑅_ESRLC Variations

Figure 11

Nominal steady-state snapshot of inductor current 𝑖_𝐿 and output voltage 𝑣_𝑂 ripples (inset) for the proposed solution and experimental 𝑅_ESRLC stability space for both the proposed dual- and state-of-the-art single-mode boost ΣΔ converters.