One Clock-Cycle Response 0.5 m CMOS Dual-Mode DC-DC Bypass Boost Converter Stable over Wide Variations
Power supplies in portable applications must not only conform and adapt to their highly integrated on-chip and in-package environments but also, more intrinsically, respond quickly to fast load dumps to achieve and maintain high accuracy. The frequency-compensation network, however, limits speed and regulation performance because it must cater to all combinations of filter capacitor , inductor L, and 's equivalent series resistance resulting from tolerance and modal design targets. As such, it must compensate the worst-case condition and therefore restrain the performance of all other possible scenarios, even if the likelihood of occurrence of the latter is considerably high and the former substantially low. Sigma-delta () control, which addresses this issue in buck converters by easing its compensation requirements and offering one-cycle transient response, has not been able to simultaneously achieve high bandwidth, high accuracy, and wide compliance in boost converters. This paper presents a dual-mode boost bypass converter, which by using a high-bandwidth bypass path only during transient load-dump events was experimentally 1.41 to 6 times faster than the state of the art in current-mode boost supplies, and this without any compromise in compliance range (0–50 m, 1–30 H, and 1–350 F).
In portable applications like cellular phones, PDAs, and the like, integrated BiCMOS and CMOS switching dc-dc supply circuits reduce cost, size, component count, and design complexity (from a user’s perspective). One of the critical bottlenecks in obtaining a fully integrated solution, however, is the frequency-compensation circuit, which is designed around off-chip power LC filter devices to obtain optimal performance . The fact is mode-rich state-of-the-art applications, manufacturing tolerances, and parameter drifts expose dc-dc converter integrated circuits (ICs) to wide variations in output capacitance CO, power inductance L, and CO’s equivalent series resistance , inducing considerable changes in loop-gain and transient response, compromising feedback stability or transient response. As a result, to guarantee stability and high bandwidth with a fixed on-chip frequency-compensation circuit, the design necessarily constrains LC values within a narrow target range . This is especially detrimental in compact high-performance multiple input-output converters [2, 3], where the on-chip or in-package LC filter is variable by design to dynamically accommodate the diverse loading conditions of the system.
Unclocked or asynchronous sigma-delta () buck converters [4–8] are self-compensating and free of the speed-stability tradeoffs of most dc-dc converters because the control loop in these converters resembles current-mode control by indirectly sensing the inductor current ripple via the ripple voltage it drops across CO’s . In other words, the ESR voltage mostly sets the terminal ripple voltage of CO, impressing the inductor ripple current information on the output voltage and achieving current-mode-like control. The resulting single-pole-like response yields higher bandwidth and more explicit control over the output ripple voltage .
Extending this technique and its benefits to boost converters, which are popular in portable electronics for boosting battery voltages to 3.3–5 V, is not straightforward because the inductor current does not fully flow to CO. Consequently, in realizing control in boost converters, the feedback circuit must explicitly sense and mix inductor current with the sensed output voltage . Such techniques, however, resurrect the limiting speed-stability tradeoffs control averted in buck converters in the first place, forcing the designer to adjust current and voltage gains thereby reducing the loop bandwidth in order to accommodate largeLC filter values.
This paper presents a dual-mode boost bypass controller IC that overcomes the aforementioned speed-stability compromise by introducing a high-speed bypass mode (and circuit) that engages only during transient load-dump events, achieving both high bandwidth and wide LC compliance. To this end, Section 2 first reviews and discusses the stability requirements of converters and their resulting transient response to fast load dumps. Section 3 then describes the proposed dual-mode technique and the design of its IC-prototype embodiment, followed by experimental results in Section 4; Section 5 draws relevant conclusions.
2.1. Control in Buck Converters
Abuck converter, as shown in Figure 1, controls the frequency and duty cycle of PMOS switch SM by comparing rippling output voltage vO via sensed voltage S against dc reference with comparator CPV. Operationally, ac inductor ripple current il flows into CO and its (which is relatively large in these converters at 100–250 m to ensure its voltage —— overwhelms ac capacitor voltage vc)  as capacitor displacement current ic, forcing ac output ripple voltage vo to mimic il (voil). As a result, in regulating vo, the converter also regulates il, which in the process simplifies the frequency response of the converter to that of a single-pole system, as in current-mode control, guaranteeing stability, irrespective of LC values.
In a positive load-step transient event, when load current iO suddenly rises, comparator CPV detects the voltage droop the now larger iO induces on vO and consequently switches SM on indefinitely (i.e., at 100% duty cycle) until vO returns within CPV’s predefined hysteretic window limits, that is, within an acceptably low margin of . During SM’s on time, the inductor voltage being nearly constant at VIN − VO, inductor current iL slews in a single switching cycle until it fully supplies iO and recharges CO back to . In other words, only the inductor and capacitor slew-rate limits and second-order delays across the comparator and switch set the response time (effective bandwidth) of the system. Note a negative load dump undergoes a similar but reversed response.
2.2. Control in Boost Converters
Unlike buck converters, ac inductor ripple current il in boost converters does not flow completely to output capacitor CO because reverse-biased diode D (shown in Figure 2) temporarily disconnects L from vO (and CO) when switch SM conducts all of iL to ground. The resulting ac ripple voltage in vO does not fully reflect the behavior of il, as it does in buck converters with nonnegligible values, which means that control in boost converters cannot rely on vO alone . The negative feedback loop in a boosting supply must therefore sense, scale, and mix iL with vO explicitly (e.g., mix iLRIgmi and vOgmv into RS as scaled sum ) to achieve current-mode-like control characteristics. A hysteretic comparator then modulates SM’s frequency and duty cycle based on how the scaled sum () of the ripples compares against a user-defined hysteresis window. Note the voltage feedback loop modulates the effective inductor reference current /RI, which is also the average inductor current IL (or low-pass filtered —LPF— version of iL) to whatever is necessary to fully supply iO.
Within the context of averaged small-signal analysis, the relatively high-gain, low-bandwidth voltage control loop (V Loop) of the system effectively embeds a higher bandwidth, lower gain current loop (I Loop), as shown Figure 3 . At low frequencies, below low-pass filter pole , iLRI nearly equals and the gain of the current loop is practically zero, but increasing with frequency until reaching its highest possible gain at frequencies past The current loop’s gain again drops at high frequencies, past the complex LC double poles, when the ac voltage across L decreases. Given that iL is, for all practical purposes, regulated to higher frequencies and therefore is a current source to the outer voltage loop at moderate-to-high frequencies, CO and effective load resistance RO set the dominant low-frequency pole of the system while L and RO invoke right-half plane zero .
For stable conditions to prevail, the unity-gain frequency of the voltage loop (i.e., the system ——) must fall below and iL must remain a current source (i.e., current loop must stay closed with considerable loop gain) for the frequency range of interest to the voltage loop . As such, must stay below both and current-loop bandwidth : or where DM is the duty-cycle of SM, is (1DM), and M is the modulator gain. Note that and shift to lower frequencies with increasing inductance values, which means that must also decrease accordingly, in an ideal case. LPF pole , whose location indicates the lowest frequency at which the current loop is closed, must also be below the worst-case value of to ensure there is enough gain for iL to remain a current source: Ultimately, the system responds to a load dump at the speed of the voltage loop, whose bandwidth is , allowing switch SM to cycle multiple times before restoring vO back to its target window. LPF pole limits the extent to which iL naturally responds to a load dump by allowing moderate-to-high frequency ac error-correcting signals through the current loop. In other words, the current loop limits (while attempting to regulate) the rising and falling rates of average iL below iL’s maximum possible slew-rates of VIN/L and (vO – VIN)/L. Because and both decrease with increasing L, with the former also decreasing with decreasing CO, the worst-case LC combination, from the perspective of stability, occurs at the highest L and lowest CO, the condition for which gains RIgmiRS and gmvRS and pole are adjusted and transient-response performance over the entire LC filter range is sacrificed.
3. Proposed Dual-Mode Controller IC
The proposed boost controller IC in Figure 4 overcomes the transient-response degradation associated with the worst-case LC combination by bypassing the main voltage loop (and its ) with a fast (and lower low-frequency loop gain) feed-forward path only during transient events. The stability requirements of the main loop set the acceptable LC range for the system while the high-bandwidth bypass path allows the system to respond in one cycle at the maximum possible inductor current slew rate, the response of which is similar to buck converters. The transient improvement is achieved on chip (i.e., without an off-chip frequency compensation circuit) and without sacrificing LC compliance.
3.1. Steady-State and Bypass Operation
The basic objective of the bypass mode is to override nominal equivalent average inductor current reference (/RI) to a higher value almost instantly only during load dumps and allow the bypass voltage loop to control and limit how much of the extra current in L flows to vO. Initially, during steady-state conditions, the bypass circuit is inactive and load current iO and SM’s average off duty cycle (i.e., one minus SM’s average on duty cycle DM) set the nominal average inductor current required to support a given iO, which is higher than iO because SM steers a portion of iL away from vO to ground according to DM: In the bypass mode, however, independent loops regulate iL to a value higher than and sensed output voltage vS to , as depicted in the equivalent circuit of Figure 5.
The current loop, which modulates switching frequency fSW and SM’s duty cycle dM, has higher bandwidth and appears as a current source for frequencies of interest to the lower bandwidth bypass voltage loop controlling auxiliary switch SA. In the bypass mode, inductor current iL is regulated at a value IPK or VPK/RI that is greater than (i.e., IL required to support IO). This means, unless otherwise limited, average diode current ID is now higher than IO, as a result of which CO recharges quickly. Once vO is back within the hysteretic window limit of bypass comparator CPB and about to surpass its upper boundary, CPB and SA divert excess current away from through SA until iO again discharges vO to CPB’s lower window limit. The switching cycle repeats as average inductor current IL gradually drops back to , at which point the bypass loop stops switching and SA remains open. Note as long as IL exceeds , the bypass voltage loop, by independently regulating vO with higher loop gain than the current loop, ensures that the voltage inputs of summing comparator CPS are virtually short-circuited (i.e., vS≈), as shown in Figure 6, allowing CPS to regulate iL exclusively.
With respect to stability, as already mentioned, the unity-gain frequency of the current loop () must exceed that of the bypass voltage loop () so the inductor appears as a current source in the voltage loop, eliminating the complex conjugate pair associated with LC in the voltage loop . Because the unity-gain bandwidth of a loop is its switching frequency, SM’s switching frequency () must exceed that of SA (). Therefore, since depends on the rising and falling rates of iLRI as it traverses CPS’s hysteretic current window HI, and on how fast excess iD (i.e., IL – ID) and IO charge and discharge output capacitor CO between CPB’s hysteretic voltage window HV, to force to be greater than , CO must exceed where the R1-R2 divider represents the effect of the resistive feedback factor on HV and the minimum stable output capacitance.
3.2. Transient Response and Mode Transition
During a positive load-dump event, when IO suddenly rises and vO droops in response, as shown in Figure 7, the dual-mode converter enters its bypass mode, raising iL to peak value IPK (or VPK/RI) in a single switching cycle of SM. Subsequently vO (or vS) is pulled back to (R1+R2)/R2 (or ) in a single switching cycle of SA. Transient-detect comparator CPT in Figure 4 perceives the load dump and engages the bypass mode by sensing when vS drops below by a preset threshold value of (e.g., 2.5% of ) (after the delay the comparator requires to switch: td). Then, CPT clamps to peak voltage VPK, the value of which sets the maximum current the circuit can drive. Switch SM therefore remains closed () until iL reaches VPK/RI (IPK), the new value of /RI. After SM resumes switching and regulating iL about IPK, SA remains open and allows all diode current iD to flow to vO until CO recharges to (HV/2)(R1R2)/R2. Beyond this point, CPB and SA regulate vS about by switching SA, in other words, by steering excess inductor current away from CO.
Ultimately, output voltage vO droops in response to load dump iO until reaches IPK. First, excess current iO discharges CO during delay td while vS reaches . Then, while SM raises iL from (or /RI or ) to IPK(or VPK/RI), iD is zero and full load current IO discharges CO, yielding a total variation (vO) of Note that the ratio of L and CO sets the dominant part of .
Once sensed output voltage vS is within the hysteretic voltage window of CPB, to transition back to steady state, must somehow fall back to whatever value () is necessary to sustain IO, reducing to zero the amount of excess current iL that bypass comparator CPB steers away from vO through SA. To that end, introducing a series negative offset voltage , as shown in Figure 8, ensures that iL is always above its target (i.e., is greater than /RI), forcing the loop to gradually decrease both and the excess current. Finally, when iL is low enough to be able to fully supply iO, and the excess current (IL–IO) is zero, the bypass loop stops switching (i.e., disengages), which means that the main voltage loop now regulates vO via SM (Figure 4) to its target. In other words, henceforth, equals . Note that the transition is continuous, allowing SA to stop switching without incurring irregularities in SM.
During a negative load dump, when iO suddenly drops, as also shown in Figure 7, automatically exceeds its new steady-state target and vO rises above its target. As a result, bypass comparator CPB engages and diverts current away from vO until vS again drops to –HV/2 (in one cycle of SA). The circuit gradually transitions back to steady state in the same manner as described earlier, through .
4. Experimental Results and Discussion
4.1. IC Design
The proposed dual-mode bypass converter was designed, fabricated, and evaluated using a 0.5m, 5 V CMOS process. The circuit embodiment of the converter, as shown in Figure 9, employs a differential-signal processing scheme to attenuate the effects of substrate noise on the high-bandwidth loops . For simplicity, series resistor RI senses iL with the understanding more power efficient techniques are possible and recommended . Current-sense amplifier ADI, which monitors the voltage across RI, includes an internal RC filter that generates differential current reference . Differential preamplifier ADV buffers and amplifies sensed output voltage vS by 5V/V to decrease the effects of offsets and hysteretic window limits in posterior amplifiers and comparators on vS and vO (i.e., improve accuracy); ADV drives differential summing amplifier ADS, bypass hysteretic comparator CPB, and transient-detect hysteretic comparator CPB.
For ease of design and reliability, main, bypass, and transient-detect comparators CPM, CPB, and CPT adopt the same circuit architecture, which is designed to yield a hysteretic window of 140 mV. The bypass threshold voltage (VBP) is composed of half the comparator hysteretic window plus an additional offset of 50 mV () that is added between CPB and CPT. Differential current-sense amplifier ADI includes a 40 mV offset voltage () at its output to ensure iL is below its target by /RI during the bypass mode, to gradually transition back to steady state after a load dump. The designed offsets are sufficiently large to dwarf the transistor mismatch-induced offsets in ADI, CPB, and CPT and ensure that the polarities of and remain unchanged across process and temperature corners.
In the absence of deep-N or buried layer isolation structures, the bulk of a single PMOS transistor serving the function of auxiliary switch SA could not be connected to the highest potential (vO) because of latch-up concerns. Whenever the switching node flies above vO following the turn-off of SM, SA’s body diode can conduct engaging the parasitic vertical PNP transistor present, channeling considerable current to the substrate. A second PMOS device is therefore added in series to use its reverse-biased body diode to block the foregoing current. And during normal operating conditions, when vO is higher than VIN, as the body diode of the first blocks the current of the second.
The proposed controller 0.5m IC was designed to supply power from a 2.7–4.2 V Li-Ion battery and drive a 0-1 A load at 5V 5% with as wide an LC range as possible (0–50 m, 1–30H, and 1–350L was achieved). The total silicon surface area the IC occupied was mm (Figure 10). The peak efficiency of the converter was 93% at 0.4A with a biasing quiescent current of 1.5 mA. The total output voltage variation of the converter in response to a 0.1–1A load dump (iO) with 5 m, 5.6 H, and 53 F of LC was 200 mV, which constitutes a 4x improvement over its nonbypassed counterpart under similar conditions (800 mV).
4.2. LC Compliance
The measured LC space for which the converter was stable is 0–50 mΩ, 1–30H, and 1–350F, as illustrated in Figure 11. This range was determined by subjecting the converter to 0.1–1A load dumps with 100 nanoseconds rise and fall times. The stability limit was observed as a loss of regulation for the proposed converter in the bypass mode, as the bypass loop was no longer able to control the loop, and subharmonic oscillations for the nonbypassed (state-of-the-art) boost converter .
The stability limits for both converters, with and without the bypass path, are reached when their respective current-loop bandwidths () approach their voltage-loop counterparts ( and ), as that is when L ceases to be a current source for the voltage loop, be the main loop, or the bypass loop. As a result, because and increase with decreasing CO and increasing IO and and RHP zero decrease with increasing L and decreasing VIN, the highest L-IO(30 H–1A) and lowest CO-VIN (12 F-2.7 V) combination constitutes worst-case conditions. Since essentially introduces a left-half plane zero in the voltage loop, increasing also increases and , which means that the above-mentioned limits along with the highest value (50 m) describe the worst-case stability point of the converter. In other words, increases with increasing L, IO, and and decreasing VIN.
The maximum capacitance was limited to 350 F as a practical limit for the intended portable application space (the circuit is stable at higher CO values). Similarly, the maximum value was limited to 50 m to keep the output voltage ripple acceptably low under a 1 A load. Under these conditions and constraints, the stability spaces for the proposed and the state-of-the-art converters are approximately equal in “volume.”
4.3. Transient Load-Dump Performance
As shown in Figure 12(a), the transient-response variation of () in response to 0.1–1A load dumps () with 100 nanoseconds rise and fall times under 2.7 V, 5.6 H, 53F, and 5 m of , L, , and was 200 mV for the proposed dual-mode scheme and 800 mV for its single-mode state-of-the-art counterpart. While the proposed converter responds by increasing above its target (to or ) in one switching cycle of , the state-of-the-art circuit increases gradually, pulling back to regulation in several cycles of , which is why the proposed solution exhibits a fourfold improvement over its predecessor. In a negative load-step (Figure 12(b)), while the excess inductor current is immediately bypassed by switch in the proposed converter keeping the output voltage overshoot low (75 mV), the excess inductor energy causes a large voltage overshoot (600 mV) in the state-of-the-art converter.
Decreasing (increasing) L increases (decreases) the rate at which iL responds to a load dump, as shown in Figure 13, thereby decreasing (increasing) the time slews (reducing ). Similarly, increasing (decreasing) decreases (increases) ’s droop rate in response to a load dump (Figure 14). Note that increasing (decreasing) also increases (decreases) the delay time between the load step and the onset of bypass threshold voltage (Figure 7), which is why the onset of rising shifts with .
Although transient-response performance for the proposed dual-mode scheme improves with decreasing L, the same is not true for the single-mode converter whose response time is limited by the bandwidth of the loop, not L’s slew rate. As a result, as illustrated in Figure 15, the percentage improvement that the dual-mode enjoys over its single-mode counterpart increases with decreasing L: 6- and 1.43-fold improvement at 1H–36F and 30H–36F, respectively.
Increasing decreases vO’s transient droop in both converter cases, except that bypass threshold voltage VBP effectively limits the extent to which a larger decreases in the proposed scheme. In the limit, increasing to such an extent that is less than would prevent the bypass mode from ever engaging. As a result, the performance improvement in is lower between the proposed and state-of-the-art solutions at higher values: for the proposed and state of the art asymptotically converge as increases.
4.4. Mode Transition
Figures 16 and 17 illustrate how the proposed dual-mode bypass boost converter transitions from steady state to bypass mode and back in response to positive and negative 0.1–0.6A load dumps with an LC combination of 15H and 53 F. As designed, the bypass mode ripple is larger at 70 mV ((/2)()/() 140 mV/2) or 1.4% than the steady-state counterpart, which is at 15 mV or 0.3%. During a positive load dump (Figure 16), when iO suddenly rises, a load-induced drop in exceeding the limit engages the bypass mode and increases to 2.5 A () in one switching cycle of . As determined by offset , the circuit then takes approximately 2.5 ms to gradually decrease back to its new target of roughly 1.3A, at which point stops switching and the converter is back in steady state. During a negative load dump (Figure 17), is automatically above its target and consequently starts diverting some of back to almost immediately, until 2.5 ms later, when drops to its new target.
The main drawbacks of the auxiliary bypass path are the silicon real estate, power, and switching noise associated with power switch . The latter two shortcomings, however, are more often than not inconsequential because they only occur during transient events, which are typically sporadic, short, and seldom occur without significantly affecting the steady-state power efficiency (Figure 18). The prominent disadvantage of the proposed solution is therefore additional silicon real estate for because it carries substantial current. The transient-performance benefits of and the bypass path that drives it, however, offset this cost.
A dual-mode bypass boost dc-dc controller 0.5m CMOS IC that is stable for an LC filter range of 0–50 m, 1–30 H, and 1–350 F and responds to positive and negative load dumps in one switching cycle has been proposed, designed, fabricated, and evaluated. The driving feature of the foregoing solution is a robust on-chip (i.e., smooth transitioning) bypass path that responds only during transient load dumps. While the converter increases inductor current iL in one switching cycle in response to a sudden rise in load current iO and uses it to quickly slew output capacitor CO back to its target, it also limits how much of iL flows to in the case of a negative load dump, when drops, limiting the total transient variation of output voltage and therefore improving accuracy performance. The transient-response benefits of the proposed scheme, as compared to state-of-the-art single-mode converters, are the highest at low values of L (e.g., 6x at 1H and 1.41x or 40% improvement at 30H) because L limits how fast rises and falls to its targets. The main drawback of the proposed technique is the additional silicon real estate required for auxiliary power switch , which is partially (and often completely) offset by its improved accuracy performance. In summary, the proposed dual-mode bypass boost converter is fast, widely LC compliant (robust), and easily implementable.
This work was supported by Texas Instruments.
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