One Clock-Cycle Response 0.5 𝜇m CMOS Dual-Mode ΣΔ DC-DC Bypass Boost Converter Stable over Wide 𝑅_ESRLC Variations

Figure 12

Measured transient performance of the proposed dual-mode and state-of-the-art single-mode ΣΔboost converters in response to (a) 0.1–1 A and (b) 1–0.1 A load steps.

(a)

(b)