Research Article

One Clock-Cycle Response 0.5  𝜇 m CMOS Dual-Mode Σ Δ DC-DC Bypass Boost Converter Stable over Wide 𝑅 E S R L C Variations

Figure 13

Measured effects of L on the transient performance of the proposed dual-mode Σ Δ bypass boost in response to 0.1–1 A load dumps, 𝐶 𝑂 = 5 3 𝜇 F .
253508.fig.0013