One Clock-Cycle Response 0.5 𝜇m CMOS Dual-Mode ΣΔ DC-DC Bypass Boost Converter Stable over Wide 𝑅_ESRLC Variations

Figure 16

Measured steady state to bypass and back transitions in response to positive 0.1–0.6 A load dumps (positive Δ𝑖_𝑂).