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Active and Passive Electronic Components
Volume 14, Issue 4, Pages 199-218
http://dx.doi.org/10.1155/1992/13545

Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits

1National Technical University of Athens, Dep. of Electrical Engineering, Div. of Computer Science, Zographou, Athens GR-15773, Greece
2GEC-Plessey Semiconductors, Tamerton Road, Roborough, Devon, Plymouth PL6 7BQ, UK

Received 7 April 1991; Accepted 5 July 1991

Copyright © 1992 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

A method for the electrical parameters analysis and modelling of lossy-coupled multilayer on-chip interconnection lines at high bit rates is presented in detail. It can be used by the VLSI designer to analyze on-chip interconnections with linear, as well as nonlinear/time varying terminators and to simulate the pulse propagation characteristics in high-speed integrated circuits. First the capacitance, inductance, conductance and resistance matrices per unit length for the given multiconductor geometry is computed. A multiple coupled line model consisting of uncoupled lossy transmission lines and linear dependent current and voltage sources if finally calculated according to the capacitance, inductance, conductance and resistance matrix values computed.