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Design Tradeoff of Hot Carrier Immunity and Robustness in LDMOS with Grounded Gate Shield
LDMOS devices with grounded gate shield structures variations were simulated and tested, aiming to address hot carrier immunity and robustness concurrently. Optimal configuration of grounded gate shield structure was found to reduce local electrical field strength at gate-to-drain overlap for better hot carrier immunity, and to achieve uniform E-field distribution on drain side for robustness as well. Design trade off of hot carrier immunity (HCI) and robustness is analyzed by simulation and silicon data.
BDD-Based Topology Optimization for Low-Power DTIG FinFET Circuits
This paper proposed a logic synthesis method based on binary decision diagram (BDD) representation. The proposed method is optimized for dual-threshold independent-gate (DTIG) FinFET circuits. The algorithm of the BDD-based topology optimization is stated in detail. Some kinds of feature subgraph structures of a BDD are extracted by the extraction algorithm and then fed to mapping algorithm to get a final optimized circuit based on predefined DTIG FinFET logic gates. Some MCNC benchmark circuits are tested under the proposed synthesis method by comparing with ABC, DC tools. The simulations show that the proposed synthesis method can obtain performance improvement for DTIG FinFET circuits.
Improving Linearity and Robustness of RF LDMOS by Mitigating Quasi-Saturation Effect
This paper discusses linearity and robustness together for the first time, disclosing a way to improve them. It reveals that the nonlinear transconductance with device working at quasi-saturation region is significant factor of device linearity. The peak electric field is the root cause of electron velocity saturation. The high electric field at the drift region near the drain will cause more electron-hole pairs generated to trigger the parasitic NPN transistor turn-on, which may cause failure of device. Devices with different drift region doping are simulated with TCAD and measured. With LDD4 doping, the peak electric field in the drift region is reduced; the linear region of the transconductance is broadened. The adjacent channel power ratio is decreased by 2 dBc; 12% more power can be discharged before the NPN transistor turn-on, indicating a better linearity and robustness.
Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits
Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Oscillator) based on complementary inverter is also used to remove passive components reducing the size of the circuit.
High Voltage Ride through Control of PMSG-Based Wind Turbine Generation System Using Supercapacitor
Regarding PMSG-based wind turbine generation system, this paper proposes a supercapacitor energy storage unit (SCESU) which is connected in parallel with the DC-link of the back-to-back converter to enhance its high voltage ride through performance. The analysis of the operation and control for the grid-side converter and SCESU are conducted. Based on real time digital simulators (RTDS), a model and a Hardware-in-the-Loop (HiL) platform of PMSG-based wind turbine with SCESU is developed, and the simulation results show that the SCESU absorbs the imbalanced energy and the grid-side converter absorbs inductive reactive power during the period of voltage swell and verify the correctness and feasibility of the high voltage ride through control strategy.
Preparation and Characterization of Printed LTCC Substrates for Microwave Devices
A novel LTCC substrate manufacturing process based on 3D printing was investigated in this paper. Borosilicate glass-alumina substrates with controlled size and thickness were successfully manufactured using a self-developed dual-nozzle hybrid printing system. The printing parameters were carefully analyzed. The mechanical and dielectric properties of the printed substrate were examined. The results show that the printed substrates obtain smooth surface (Ra=0.92 μm), compact microstructure (relative density 93.7%), proper bending strength (156 mPa), and low dielectric constant and loss (Ɛr=6.2, =0.0055, at 3 GHz). All of those qualify the printed glass–ceramic substrates to be used as potential LTCC substrates in the microwave applications. The proposed method could simplify the traditional LTCC technology.