Development of a 100 mW-Class 94 GHz High-Efficiency Single-Series Rectifier Feed by Finline for Micro-UAV ApplicationRead the full article
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The Design of an Ultralow-Power Ultra-wideband (5 GHz–10 GHz) Low Noise Amplifier in 0.13 μm CMOS Technology
The calculation and design of an ultralow-power Low Noise Amplifier (LNA) are proposed in this paper. The LNA operates from 5 GHz to 10 GHz, and forward body biasing technique is used to bring down power consumption of the circuit. The design revolves around precise calculations related to input impedance, output impedance, and the gain of the circuit. MATLAB and Advanced Design System (ADS) are utilized to design and simulate the LNA. In addition, TSMC 0.13 μm CMOS process is used in ADS. The LNA is biased with two different voltage supplies in order to reduce power consumption. Noise Figure (NF), input matching (S11), gain (S21), IIP3, and power dissipation are 1.46 dB–2.27 dB, −11.25 dB, 13.82 dB, −8.5, and 963 μW, respectively.
Four-Port Dual-Mode Diplexer with High Signal Isolation
An ease of four-port dual-mode diplexer with high signal isolation is presented. A compact dual-mode diplexer with high signal isolation between the Rx and Tx modules is achievable by only using one resonator filter topology. Two back-to-back dual-mode diplexers have a 180° phase shift in one branch. The high isolation can be achieved by amplitude and phase cancellation technique. The delayed transmission line can be easily achieved by the phase shifter. The simulated and measured four-port dual-mode diplexers are designed at the centre frequency of Rx/Tx at 1.95 GHz and 2.14 GHz, respectively. The measured results of Rx/Tx dual-mode diplexer devices are presented with 47.1 dB Rx/Tx isolation. This four-port dual-mode diplexer achieves the isolation (S32) of more than 24.1 dB when compared with the conventional three-port dual-mode diplexer structure.
Design Tradeoff of Hot Carrier Immunity and Robustness in LDMOS with Grounded Gate Shield
LDMOS devices with grounded gate shield structures variations were simulated and tested, aiming to address hot carrier immunity and robustness concurrently. Optimal configuration of grounded gate shield structure was found to reduce local electrical field strength at gate-to-drain overlap for better hot carrier immunity, and to achieve uniform E-field distribution on drain side for robustness as well. Design trade off of hot carrier immunity (HCI) and robustness is analyzed by simulation and silicon data.
BDD-Based Topology Optimization for Low-Power DTIG FinFET Circuits
This paper proposed a logic synthesis method based on binary decision diagram (BDD) representation. The proposed method is optimized for dual-threshold independent-gate (DTIG) FinFET circuits. The algorithm of the BDD-based topology optimization is stated in detail. Some kinds of feature subgraph structures of a BDD are extracted by the extraction algorithm and then fed to mapping algorithm to get a final optimized circuit based on predefined DTIG FinFET logic gates. Some MCNC benchmark circuits are tested under the proposed synthesis method by comparing with ABC, DC tools. The simulations show that the proposed synthesis method can obtain performance improvement for DTIG FinFET circuits.
Improving Linearity and Robustness of RF LDMOS by Mitigating Quasi-Saturation Effect
This paper discusses linearity and robustness together for the first time, disclosing a way to improve them. It reveals that the nonlinear transconductance with device working at quasi-saturation region is significant factor of device linearity. The peak electric field is the root cause of electron velocity saturation. The high electric field at the drift region near the drain will cause more electron-hole pairs generated to trigger the parasitic NPN transistor turn-on, which may cause failure of device. Devices with different drift region doping are simulated with TCAD and measured. With LDD4 doping, the peak electric field in the drift region is reduced; the linear region of the transconductance is broadened. The adjacent channel power ratio is decreased by 2 dBc; 12% more power can be discharged before the NPN transistor turn-on, indicating a better linearity and robustness.
Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits
Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Oscillator) based on complementary inverter is also used to remove passive components reducing the size of the circuit.