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Active and Passive Electronic Components
Volume 14, Issue 4, Pages 199-218
http://dx.doi.org/10.1155/1992/13545

Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits

1National Technical University of Athens, Dep. of Electrical Engineering, Div. of Computer Science, Zographou, Athens GR-15773, Greece
2GEC-Plessey Semiconductors, Tamerton Road, Roborough, Devon, Plymouth PL6 7BQ, UK

Received 7 April 1991; Accepted 5 July 1991

Copyright © 1992 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

K. Z. Dimopoulos, J. N. Avaritsiotis, and S. J. White, “Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits,” Active and Passive Electronic Components, vol. 14, no. 4, pp. 199-218, 1992. https://doi.org/10.1155/1992/13545.