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Active and Passive Electronic Components
Volume 18 (1995), Issue 3, Pages 179-202

Vlsi Interconnection Modelling Using a Finite Element Approach

IETE, India

Copyright © 1995 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In the last decade, an important shift has taken place in the design of hardware with the advent of smaller and denser integrated circuit packages. Analysis techniques are required to ensure the proper electrical functioning of this hardware. An efficient method is presented to model the parasitic capacitance of VLSI (very large scale integration) interconnections. It is valid for conductors in a stratified medium, which is considered to be a good approximation for the SiSiO2 system of which present day ICs are made. The model approximates the charge density on the conductors as a continuous function on a web of edges. Each base function in the approximation has the form of a “spider” of edges. Here the method used [1] has very low complexity, as compared to other models used previously [2], and achieves a high degree of precision within the range of validity of the stratified medium.