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Active and Passive Electronic Components
Volume 2012 (2012), Article ID 181395, 11 pages
Research Article

Novel Power Reduction Technique for ReRAM with Automatic Avoidance Circuit for Wasteful Overwrite

1School of Electrical and Computer Engineering, College of Science and Engineering, Kanazawa University, Kakuma, Kanazawa 920-1192, Japan
2School of Health Sciences, College of Medical, Pharmaceutical and Health Sciences, Kanazawa University, 5-11-80 Kodatsuno, Kanazawa 920–0942, Japan

Received 18 October 2011; Accepted 5 January 2012

Academic Editor: Daisaburo Takashima

Copyright © 2012 Takaya Handa et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Low-power operations can be great advantageous for ReRAM devices. However, wasteful overwriting such as the SET operation to low-resistance state (LRS) device and the RESET operation to high-resistance state (HRS) device causes not only an increase in power but also the degradation of the write cycles due to repeatedly rewriting. Thus, in this paper, we proposed a novel automatic avoidance circuit for dealing with wasteful overwriting that uses a sense amplifier and estimated the energy consumption reduction rate by conducting a circuit simulation. As a result, this circuit helped to reliably avoid the wasteful overwriting operation to reduce about 99% and 97% of wasteful energy using VSRC and CSRC, respectively.