Novel Power Reduction Technique for ReRAM with Automatic Avoidance Circuit for Wasteful Overwrite

Figure 11

Simulation results.

(a) I-V (initial low): VSRC

(b) I-V (initial high): VSRC

(c) VSRC out (initial low)

(d) VSRC out (initial high)

(e) I-V (initial low): CSRC

(f) I-V (initial high): CSRC

(g) CSRC out (initial low)

(h) CSRC out (initial high)