Gate Stack Engineering and Thermal Treatment on Electrical and Interfacial Properties of Ti/Pt/HfO<sub>2</sub>/InAs <i>p</i>MOS Capacitors

<table>1 MHz temperature-dependent <svg height="11.75" id="M46" style="vertical-align:-0.23206pt" version="1.1" viewbox="0 0 12.1125 11.75" width="12.1125" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,0,0,-.017,.062,11.4)"><path d="M682 629q-1 -16 -1.5 -72t-2.5 -86l-31 -4q-5 92 -51 129t-139 37q-100 0 -177 -49t-116 -125t-39 -162q0 -122 66 -201t182 -79q83 0 137 42.5t112 128.5l26 -15q-12 -31 -42.5 -88t-45.5 -75q-139 -27 -199 -27q-148 0 -243 81.5t-95 226.5q0 173 129.5 274.5
t325.5 101.5q114 0 204 -38z" id="x1D436"></path></g>
</svg>-<svg height="11.375" id="M47" style="vertical-align:-0.1638pt" version="1.1" viewbox="0 0 12.7375 11.375" width="12.7375" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,0,0,-.017,.062,11.113)"><path d="M730 650l-8 -28q-52 -4 -72 -18t-64 -77q-79 -113 -321 -539h-33l-119 541q-13 59 -29.5 73t-66.5 20l7 28h245l-8 -28l-28 -5q-33 -6 -40.5 -15.5t-0.5 -38.5l102 -450h2q191 320 246 430q21 42 15.5 56t-43.5 19l-31 4l7 28h240z" id="x1D449"></path></g>
</svg> characteristics of InAs MOS capacitor with respective InP or As-rich interfacial layers.</table>

Active and Passive Electronic Components

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Figure 7

Figure 7: Gate Stack Engineering and Thermal Treatment on Electrical and Interfacial Properties of Ti/Pt/HfO<sub>2</sub>/InAs <i>p</i>MOS Capacitors 

Active and Passive Electronic Components

Gate Stack Engineering and Thermal Treatment on Electrical and Interfacial Properties of Ti/Pt/HfO2/InAs pMOS Capacitors

Figure 7

Gate Stack Engineering and Thermal Treatment on Electrical and Interfacial Properties of Ti/Pt/HfO₂/InAs pMOS Capacitors