Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC

<table> (a) A <svg height="11.125" id="M13" style="vertical-align:-0.1638pt" version="1.1" viewbox="0 0 33.974998 11.125" width="33.974998" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,10.862)"><path d="M285 378v-2q65 -13 102 -54.5t37 -97.5q0 -57 -30.5 -104.5t-74 -75t-85.5 -42t-72 -14.5q-31 0 -59.5 11t-40.5 23q-19 18 -16 36q1 16 23 33q13 10 24 0q58 -51 124 -51q55 0 88 40t33 112q0 64 -39 96.5t-88 32.5q-29 0 -64 -11l-6 29q77 25 118 57.5t41 84.5
q0 45 -26.5 69.5t-68.5 24.5q-67 0 -120 -79l-20 20l43 63q51 56 127 56h1q66 0 107 -37t41 -95q0 -42 -31 -71q-22 -23 -68 -54z" id="x33"></path></g><g transform="matrix(.017,-0,0,-.017,11.996,10.862)"><path d="M528 54l-36 -38l-198 201l-198 -201l-36 38l197 200l-197 201l36 38l198 -202l198 202l36 -38l-197 -201z" id="xD7"></path></g><g transform="matrix(.017,-0,0,-.017,25.748,10.862)"><path d="M412 140l28 -9q0 -2 -35 -131h-373v23q112 112 161 170q59 70 92 127t33 115q0 63 -31 98t-86 35q-75 0 -137 -93l-22 20l57 81q55 59 135 59q69 0 118.5 -46.5t49.5 -122.5q0 -62 -29.5 -114t-102.5 -130l-141 -149h186q42 0 58.5 10.5t38.5 56.5z" id="x32"></path></g>
</svg> array of tile stacks. (b) A tile stack. (c) Thermal resistance model of a tile stack.</table>

Active and Passive Electronic Components

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Figure 2

Figure 2: Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC 