Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC

Table 1

The first test case.

Die	Circuit	Technology; (nm)	Die power (W)	No. of cores	No. of scan chain	No. of test pattern	TAM width; (hard-die mode)	Test time (No. of test cycles)
Die 4	Logic	180	36.0	9	15	130	17	76,440
Die 3	Logic	180	36.0	9	15	130	17	76,440
Die 2	ARM9	180	6.0	2	20	300	22	210,000
Die 1	SRAM	90	0.65	25	N/A	N/A	2	425,984
Die 0	DRAM	32	0.3	1	N/A	N/A	2	500,000