|
| Criteria | References |
| [27] | [28] | [29] | [30] | [31] |
|
| Technique | Instruction isolation | DVFS and critical path isolation under temperature variations | Variable clock in times of process variations | Soft edge flip-flop | Flow-through latch between stages and selection of different voltages |
| Technology | 45 nm | BPTM 70 nm | 90 nm | PTM 65 nm | PTM 32 nm |
| Circuit | 32-bit in-order 5-stage dual-pipeline processor with IA32 | in-order superscalar pipeline with the Alpha ISA | 32-bit microprocessor | 34-bit pipelined adder | 6 stages pipelined FPU |
| Frequency | 1.25 GHz | 1.5–3 GHz | ~0.1–1 GHz | 2–2.5 GHz | Improves BIPS/W by 47% (actual frequency not reported) |
| Area and/or frequency impact | 28% performance reduction due to instruction isolation | ~4.5% area overhead /3.4–11% frequency overhead | 2.6% area overhead/13%–50% performance improvement | 5–20% performance improvement | 40% performance improvement |
| Energy/Temperature impact | 13% power reduction | Reduces temperature by 6.6–9% | 3% energy overhead | 19% power saving (4.9 mW) | Not reported |
| Min voltage | 740 mV for ADD 680 mV for XOR and AND | 700 mV | Scaling from 1.2 V to 1 V | Scaling from 1.2 V to 1.05 V (5–20% reduction) | Scaling from 1.4 V to 0.95 V |
| Pros | DVS enabled | Temperature variations tolerant, DVFS enabled | Low energy and area overhead | Rather large power reduction | Rather large performance improvement |
| Cons | Performance reduction | PV variations not discussed | Not supporting very low voltages | Not supporting very low voltages, PVT variations not discussed | Not supporting very low voltages |
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