MCML D-Latch Using Triple-Tail Cells: Analysis and Design

Table 1

Differential output voltages of the proposed D-latch for various input combinations.

Differential inputs		Present state	Currents through the transistors						Next state differential output (𝑉𝑄−𝑉𝑄)
CLK	D	Q	M LV3	M LV4	M LV5	M LV6	M LV7	M LV8	Level	𝑅𝑃[(𝑖𝐷,4+𝑖𝐷,6)−(𝑖𝐷,3+𝑖𝐷,5)]
L	L	L	𝐼3	0	𝐼1	0	𝐼2	0	𝑉OL1	−𝑅𝑃𝐼SS/2(1+1/(1+𝑁))
L	L	H	𝐼3	0	0	𝐼1	𝐼2	0	𝑉OH2	𝑅𝑃𝐼SS/2(𝑁/(1+𝑁))
L	H	L	0	𝐼3	𝐼1	0	𝐼2	0	𝑉OL2	−𝑅𝑃𝐼SS/2(𝑁/(1+𝑁))
L	H	H	0	𝐼3	0	𝐼1	𝐼2	0	𝑉OH1	𝑅𝑃𝐼SS/2(1+𝑁/(1+𝑁))
H	L	L	𝐼1	0	𝐼3	0	0	𝐼2	𝑉OL1	−𝑅𝑃𝐼SS/2(1+𝑁/(1+𝑁))
H	L	H	𝐼1	0	0	𝐼3	0	𝐼2	𝑉OL2	−𝑅𝑃𝐼SS/2(𝑁/(1+𝑁))
H	H	L	0	𝐼1	𝐼3	0	0	𝐼2	𝑉OH2	𝑅𝑃𝐼SS/2(𝑁/(1+𝑁))
H	H	H	0	𝐼1	0	𝐼3	0	𝐼2	𝑉OH1	𝑅𝑃𝐼SS/2(1+𝑁/(1+𝑁))

L/H = low/high differential input voltage, 𝐼₁=𝐼_SS/2, 𝐼₂=(𝐼_SS/2)(𝑁/(1+𝑁)), and 𝐼₃=(𝐼_SS/2)(1/(1+𝑁)).