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Active and Passive Electronic Components
Volume 2013, Article ID 967057, 5 pages
Research Article

Current Mode Full-Wave Rectifier Based on a Single MZC-CDTA

Department of Electronics and Communications Engineering, Delhi Technological University (Formerly Delhi College of Engineering), Bawana Road, Delhi 110042, India

Received 30 March 2013; Revised 14 June 2013; Accepted 15 June 2013

Academic Editor: Ali Umit Keskin

Copyright © 2013 Neeta Pandey and Rajeshwari Pandey. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper presents a current mode full-wave rectifier based on single modified Z copy current difference transconductance amplifier (MZC-CDTA) and two switches. The circuit is simple and is suitable for IC implementation. The functionality of the circuit is verified with SPICE simulation using 0.35 μm TSMC CMOS technology parameters.

1. Introduction

The full-wave rectifiers are used in varied applications [58] such as signal-polarity detectors, averaging circuits, peak value detectors, clipper circuits, and amplitude-modulated signal detectors. Conventionally, full-wave rectifier is implemented using operational amplifiers which are not capable of operating at higher frequencies because of slew rate and fixed gain-bandwidth product limitations [9]. Current mode approach due to its inherent wide bandwidth which is virtually independent of closed loop gain, greater linearity, and large dynamic range [9] has generated lots of interest, and significant research efforts have been directed towards developing new active blocks based on this approach. Among these blocks, CDTA [1012] has received considerable attention as the external resistors may be implemented by TA block of CDTA, thereby reducing/avoiding external resistors usage in the applications based on CDTA [12] and making these suitable for on-chip implementation. Additionally, due to low input impedance terminals, CDTA is free from parasitic capacitances and hence is appropriate for high frequency operation. This has resulted in development of a wide range of CDTA-based applications [14, 1117].

A variety of FWR circuits using CDTA [14] have been reported in the literature. The CDTA-based FWR circuits presented in [13] use single CDTA, whereas configuration reported in [4] employs two CDTAs and a multiple output current follower. The structures [1, 2, 4] use four pn junction diodes, whereas two Schottky diodes are used in [3]. Additionally, auxiliary bias is employed in [1] and a grounded resistor is employed in [4]. In this paper, a new approach for designing a single CDTA-based current mode full-wave rectifier (FWR) configuration is presented. The proposed current mode FWR configuration uses a single CDTA called MZC-CDTA (modified Z copy CDTA) and two MOS switches. The features of the CDTA-based FWR circuits are summarized in Table 1. It may be noted that the proposed FWR uses similar a number of active elements as given in [3]; however, the use of MOS switches makes it more suitable from integration viewpoint. The functionality of the circuit is verified with SPICE simulations using 0.35 m TSMC CMOS technology parameters.

Table 1: Summary of available CDTA-based FWR.

2. Circuit Description

The circuit symbol of MZC-CDTA is shown in Figure 1. It is similar to ZC-CDTA except for an extra port. The port relationship of the MZC-CDTA is characterized by the following matrix: where is transconductance of the MZC-CDTA. The CMOS-based internal circuit of MZC-CDTA is depicted in Figure 2 and is based on the CDTA schematic given in [1]. The value of transconductance () is expressed as which can be adjusted by bias current of MZC-CDTA.

Figure 1: Circuit symbol of MZC-CDTA.
Figure 2: MZC-CDTA implementation.

The proposed MZC-CDTA-based full-wave rectifier is shown in Figure 3. It uses a single MZC-CDTA and two MOS switches ( and ) connected at and ports, respectively. The port being open, its voltage would approach to or depending upon the current flowing into terminal. Further, as terminal of the circuit is also not drawing any current, so for small current inputs, it would be saturating to supply voltage, resulting in At any instant, either of the two transistors and will be in ON condition as the current through and ports is out of phase. The transistor will be ON for positive input currents, whereas the negative input current will bring transistor in ON condition thereby making a unidirectional current.

Figure 3: Proposed current mode rectifier.

3. Nonideal Analysis

The actual behavior of the circuit may deviate from the ideal one due to error in current transfer from and terminals to , , and terminals and also current at and terminals. The current transfer from and ports to , , and ports may differ from unity value, and these tracking errors are represented by and . The inaccuracy in transconductance transfer from to and ports is modeled by . Considering the inaccuracies outlined earlier, the output current becomes a unidirectional current of value . Depending upon the internal structure and technology used, the tracking errors , , and also have first-order low-pass rolloff which affects the performance at high frequencies.

Apart from the error in the current transfer, there are parasitic impedances at and ports (resistances and ) and shunt output impedances (//) at ports , , ,   , and . The input current is applied at port in the proposed circuit and port is left open, so resistances at and ports do not put restriction in the behavior of the circuit. The impedances at , , , , and ports will have an impact at higher operating frequencies.

4. Simulation Results

The functionality of the proposed current mode rectifier is validated using MZC-CDTA schematic of Figure 2. The model parameters of TSMC 0.35 μm CMOS process and supply voltages of  V are used. The aspect ratios of various transistors are taken from [16], and the bias current of 60 μA is used. The circuit of Figure 3 is excited by a 10 KHz, 20 μA sinusoidal current signal. The time domain behaviour of voltage developed at port due to input current is shown in Figure 4. For positive half-cycle of the input current, a negative voltage is developed at port which in turn makes the transistor ON, whereas transistor remains OFF, and thus output current is equal to input current for positive half-cycle. The negative half-cycle of the input current makes port voltage positive and turns transistor ON. The current through transistor is out of phase with input current, and therefore the output current would be positive. The input and output currents for the proposed circuit under sinusoidal excitation are shown in Figure 5 and conform to the theoretical predictions. The simulated ripple factor curve is plotted in Figure 6 and its value is approximately 0.5. Figure 7 shows the response of the circuit under sinusoidal excitation. The simulated total power consumption of the circuit is 14 mW.

Figure 4: Time domain response of input current and port voltage.
Figure 5: Input and output waveforms for sinusoidal excitation.
Figure 6: Simulated curve for ripple factor.
Figure 7: Input and output waveforms for triangular excitation.

The DC response of the proposed circuit is also studied and the transfer characteristics are shown in Figure 6. It may be noted that the proposed circuit behavior is linear for input currents ranging between −300 μA and +300 μA. The positive and negative slopes of 0.967 and 0.993, respectively are observed. The deviation of slope from unity value may be attribute to CDTA nonidealities.

The proposed circuit is also tested to judge the level of harmonic distortion at the output of the signal. The %THD result is shown in Figure 9 which shows that the output distortion is around 22% for input currents up to 300 μA.

5. Conclusion

A single MZC-CDTA-based current mode full-wave rectifier is presented in this paper. It uses two switches. As the circuit uses only MOS transistors, it is suitable for IC implementation. SPICE simulation results using 0.35 μm TSMC CMOS technology parameters are given in support of the theory (see Figure 8).

Figure 8: DC response of the proposed circuit.
Figure 9: Percentage THD versus input bias current.


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