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Active and Passive Electronic Components
Volume 2014 (2014), Article ID 723053, 11 pages
Research Article

Implementation of Power Efficient Flash Analogue-to-Digital Converter

Department of Electronics and Communication Engineering, VFSTR University (Vignan University), Guntur, Andhra Pradesh 522 213, India

Received 16 May 2014; Accepted 2 July 2014; Published 14 August 2014

Academic Editor: Ching Liang Dai

Copyright © 2014 Taninki Sai Lakshmi et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


An efficient low power high speed 5-bit 5-GS/s flash analogue-to-digital converter (ADC) is proposed in this paper. The designing of a thermometer code to binary code is one of the exacting issues of low power flash ADC. The embodiment consists of two main blocks, a comparator and a digital encoder. To reduce the metastability and the effect of bubble errors, the thermometer code is converted into the gray code and there after translated to binary code through encoder. The proposed encoder is thus implemented by using differential cascade voltage switch logic (DCVSL) to maintain high speed and low power dissipation. The proposed 5-bit flash ADC is designed using Cadence 180 nm CMOS technology with a supply rail voltage typically ±0.85 V. The simulation results include a total power dissipation of 46.69 mW, integral nonlinearity (INL) value of −0.30 LSB and differential nonlinearity (DNL) value of −0.24 LSB, of the flash ADC.