Table of Contents Author Guidelines Submit a Manuscript
Active and Passive Electronic Components
Volume 2014, Article ID 723053, 11 pages
http://dx.doi.org/10.1155/2014/723053
Research Article

Implementation of Power Efficient Flash Analogue-to-Digital Converter

Department of Electronics and Communication Engineering, VFSTR University (Vignan University), Guntur, Andhra Pradesh 522 213, India

Received 16 May 2014; Accepted 2 July 2014; Published 14 August 2014

Academic Editor: Ching Liang Dai

Copyright © 2014 Taninki Sai Lakshmi et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. G. T. Varghese and K. K. Mahapatra, “A high speed low power encoder for a 5 bit flash ADC,” in Proceedings of the International Conference on Green Technologies (ICGT '12), pp. 41–45, Trivandrum, India, December 2012. View at Publisher · View at Google Scholar · View at Scopus
  2. M. Rahman, K. L. Baishnab, and F. A. Talukdar, “A novel ROM architecture for reducing bubble and metastability errors in high speed flash ADCs,” in Proceedings of the 20th International Conference on Electronics Communications and Computers (CONIELECOMP '10), pp. 15–19, Cholula, Mexico, February 2010. View at Publisher · View at Google Scholar · View at Scopus
  3. N. Agrawal and R. Paily, “An improved ROM architecture for bubble error suppression in high speed flash ADCs,” in Proceeding of the Annual IEEE Student Paper Conference (AISPC ’08), pp. 1–5, Aalborg, Denmark, February 2008. View at Publisher · View at Google Scholar · View at Scopus
  4. Y. Z. Lin, Y. T. Liu, and S. J. Chang, “A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS,” in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC '07), pp. 213–216, September 2007. View at Publisher · View at Google Scholar · View at Scopus
  5. S. Park, Y. Palaskas, and M. P. Flynn, “A 4-GS/s 4-bit flash ADC in 0.18 μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 42, no. 9, pp. 1865–1872, 2007. View at Publisher · View at Google Scholar · View at Scopus
  6. K. Makigawa, K. Ono, T. Ohkawa, K. Matsuura, and M. Segami, “A 7bit 800Msps 120mW folding and interpolation ADC using a mixed-averaging scheme,” in Proceeding of the Symposium on VLSI Circuits Digest of Technical Papers (VLSIC ’06), pp. 138–139, Honolulu, Hawaii, USA, June 2006. View at Scopus
  7. C. Chen and J. Ren, “An 8-bit 200-MSample/s folding and interpolating ADC in 0.25 mm2,” Analog Integrated Circuits and Signal Processing, vol. 47, no. 2, pp. 203–206, 2006. View at Publisher · View at Google Scholar · View at Scopus
  8. H. Y. Huang, Y. Z. Lin, and S. J. Chang, “A 5-bit 1 GSample/s two-stage ADC with a new flash folded architecture,” in Proceedings of the IEEE Region 10 Conference (TENCON '07), pp. 1–4, Taipei, Taiwan, November 2007. View at Publisher · View at Google Scholar · View at Scopus
  9. W. S. Chu and K. W. Current, “A CMOS voltage comparator with rail-to-rail input-range,” Analog Integrated Circuits and Signal Processing, vol. 19, no. 2, pp. 145–149, 1999. View at Publisher · View at Google Scholar · View at Scopus
  10. A. Srinivasulu and K. Sivadasan, “Optical exclusive-OR gate,” Journal of Microwaves, Optoelectronics and Electromagnetic Applications, vol. 3, no. 1, pp. 20–25, 2003. View at Google Scholar
  11. Saloni, M. Goswami, and B. R. Singh, “A 5-bit 1.5 GS/s ADC using reduced comparator architecture,” in Proceedings of the 8th International Design and Test Symposium (IDT ’13), pp. 1–3, Marrakesh, Morocco, December 2013. View at Publisher · View at Google Scholar
  12. D. W. Kang and Y.-B. Kim, “Design of enhanced differential cascade voltage switch logic (EDCVSL) circuits for high-fan-in gate,” in Proceedings of the 15 th Annual IEEE International ASIC/SOC Conference, pp. 309–313, 2002.
  13. C. C. Chen, Y. L. Chung, and C. I. Chiu, “6-b 1.6-GS/s flash ADC with distributed track-and-hold pre-comparators in a 0.18 μm CMOS,” in Proceedings of the International Symposium on Signals, Circuits and Systems (ISSCS '09), pp. 1–4, July 2009. View at Publisher · View at Google Scholar · View at Scopus
  14. L. Wu, F. Huang, Y. Gao, Y. Wang, and J. Cheng, “A 42 mW 2 GS/s 4-bit flash ADC in 0.18-μm CMOS,” in Proceeding of the International Conference on Wireless Communications and Signal Processing (WCSP ’09), pp. 1–5, Nanjing, China, November 2009. View at Publisher · View at Google Scholar · View at Scopus
  15. Z. Liu, S. Jia, Y. Wang, L. Ji, and X. Zhang, “Efficient encoding scheme for folding ADC,” in Proceedings of the 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT '08), pp. 1988–1991, Beijing, China, October 2008. View at Publisher · View at Google Scholar · View at Scopus
  16. E. Sail and M. Vesterbacka, “A multiplexer based decoder for flash analog-to-digital converters,” in Proceedings of the IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering (TENCON '04), vol. 4, pp. 250–253, November 2004. View at Publisher · View at Google Scholar · View at Scopus
  17. G. Torfs, Z. Li, J. Bauwelinck, X. Yin, G. van der Plas, and J. Vandewege, “Low-power 4-bit flash analogue to digital converter for ranging applications,” Electronics Letters, vol. 47, no. 1, pp. 20–22, 2011. View at Publisher · View at Google Scholar · View at Scopus
  18. J. Yoo, D. Lee, K. Choi, and J. Kim, “A power and resolution adaptive flash analog-to-digital converter,” in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED ’02), pp. 233–236, August 2002. View at Publisher · View at Google Scholar · View at Scopus
  19. S. Sheikhaei, S. Mirabbasi, and A. Ivanov, “A 4-Bit 5 GS/s flash A/D converter in 0.18 μm CMOS,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS ’05), vol. 6, pp. 6138–6141, May 2005. View at Publisher · View at Google Scholar · View at Scopus
  20. R. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout and Simulation, Prentice Hall, 2000.
  21. J. X. Ma, S. W. Sin, S.-P. U, and R. P. Martins, “A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '06), pp. 4305–4308, May 2006. View at Scopus
  22. P. Pallavi, N. Agarwal, Ankita, S. Kumari, and A. Srinivasulu, “Switched capacitor charge pump circuit using modified current source inverter,” in Proceedings of the 4th International Conference on Advanced Computing and Communication Technologies, pp. 826–829, 2010.
  23. D. Lee, J. Yoo, K. Choi, and J. Ghaznavi, “Fat tree encoder design for ultra-high speed flash A/D converters,” in Proceedings of the 45th Midwest Symposium on Circuits and Systems, pp. 87–90, Tulsa, Okla, USA, August 2002. View at Scopus
  24. V. Hiremath and S. Ren, “An ultra high speed encoder for 5GSPS Flash ADC,” in Proceedings of the IEEE International Instrumentation and Measurement Technology Conference (I2MTC '10), pp. 136–141, May 2010. View at Publisher · View at Google Scholar · View at Scopus
  25. K. Uyttenhove and M. S. J. Steyaert, “A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 38, no. 7, pp. 1115–1122, 2003. View at Publisher · View at Google Scholar · View at Scopus
  26. W. H. Ma, J. C. Kao, and M. Papaefthymiou, “A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution,” in Proceedings of the 37th European Solid-State Circuits Conference (ESSCIRC '11), pp. 155–158, September 2011. View at Publisher · View at Google Scholar · View at Scopus
  27. T. V. Rao and A. Srinivasulu, “Modified level restorers using current sink and current source inverter structures for BBL-PT full adder,” Radioengineering, vol. 21, no. 4, pp. 1279–1286, 2012. View at Google Scholar · View at Scopus
  28. S. Park, Y. Palaskas, A. Ravi, R. E. Bishop, and M. P. Flynn, “A 3.5 GS/s 5-b flash ADC in 90 nm CMOS,” in Proceedings of the IEEE 2006 Custom Integrated Circuits Conference (CICC ’06), pp. 489–492, San Jose, Calif, USA, September 2006. View at Publisher · View at Google Scholar · View at Scopus
  29. A. Srinivasulu and M. Rajesh, “UPLD and CPTL pull-up stages for differential cascode voltage switch logic,” Journal of Engineering, vol. 2013, Article ID 595296, 5 pages, 2013. View at Publisher · View at Google Scholar