Bus Implementation Using New Low Power PFSCL Tristate Buffers

Table 1

Summary of performance parameters for proposed and available PFSCL tristate buffers.

Tristate buffer	Parameter
	Propagation delay (ps)	Output enable time (ps)	Power (μW)	Power delay product (fJ)
Proposed topology 1	425	553	45	19.125
Proposed topology 2	419	348	45	18.855
Proposed topology 3	408	132	45	18.360
Proposed topology 4	428	438	45	19.260
Switch based buffer [11]	430	182	90	38.700