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Active and Passive Electronic Components
Volume 2017 (2017), Article ID 5947819, 8 pages
Research Article

Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET

1Department of Electronic and Communication Engineering, Guru Nanak Dev Engineering College, Ludhiana 141006, India
2Semi-Conductor Laboratory, Department of Space, Government of India, Mohali 160071, India

Correspondence should be addressed to Navneet Kaur;

Received 30 July 2016; Revised 31 October 2016; Accepted 17 November 2016; Published 21 March 2017

Academic Editor: Mingxiang Wang

Copyright © 2017 Satyam Shukla et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel length multigate MOSFETs have been considered as most promising devices and FinFETs are the leading multigate MOSFET devices. Process parameters can be varied to obtain the desired performance of the FinFET device. In this paper, evaluation of on-off current ratio (), subthreshold swing (SS) and Drain Induced Barrier Lowering (DIBL) for different process parameters, that is, doping concentration (1015/cm3 to 1018/cm3), oxide thickness (0.5 nm and 1 nm), and fin height (10 nm to 40 nm), has been presented for 20 nm triangular FinFET device. Density gradient model used in design simulation incorporates the considerable quantum effects and provides more practical environment for device simulation. Simulation result shows that fin shape has great impact on FinFET performance and triangular fin shape leads to reduction in leakage current and SCEs. Comparative analysis of simulation results has been investigated to observe the impact of process parameters on the performance of designed FinFET.