VHDL-AMS Simulation Framework for Molecular-FET Device-to-Circuit Modeling and Design

Figure 10

Crossbar architecture of a: (a) half adder implemented using complementary logic. The orange color shows a common back gate for P-type region and the green shows that for N-type region. (b) Single-bit full adder, implemented by the connection of two HAs and an OR gate. (c) Output waveforms of a 3-bit ripple carry adder implemented using complementary logic. In this case, the low and high input values of  V and  V are used to encode logic “0” and “1,” respectively.

(a)

(b)

(c)