BDD-Based Topology Optimization for Low-Power DTIG FinFET Circuits

Figure 2

(a) A BDD example representing the Boolean logic equation (1), (b)–(f) its extracted BDD subgraphs, (g) MUX realization directly from (a), (h) the AOI and OAI cells mapped by the extracted BDD subgraphs (e), and (f), (i) the optimized result.