A Novel Hardware Systolic Architecture of a Self-Organizing Map Neural Network

Table 4

Comparison of proposed SSOM architecture to previously published implementations.

Design	Size of the SOM (P × Q)	Dimx	Maximal frequency (MHz)	MCUPS	MCPS	Resources
[8] ASIC 65 nm	16 × 16	32	100	3,080	3,091	—
[17] FPGA 40 nm	256	64	79.8	—	21,845	—
[18] FPGA 28 nm	16 × 16	256	250	18,597	—	—
[24] FPGA 40 nm (virtex 6)	16 × 16	3	33	25,344	—	94,266 LUT
(SSOM) FPGA 60 nm	16 × 16	32	185	15,308	23,316	82,522 LUT
(SSOM) FPGA 40 nm			225	18,618	28,357	75,225 LUT
(SSOM) FPGA 28 nm			290	23,997	36,549	70,478 LUT