Analysis of a No Equilibrium Linear Resistive-Capacitive-Inductance Shunted Junction Model, Dynamics, Synchronization, and Application to Digital Cryptography in Its Fractional-Order Form

<div>Bifurcation diagram showing the local maxima of the state variable <svg height="6.1673pt" id="M163" style="vertical-align:-0.2063904pt" version="1.1" viewbox="-0.0498162 -5.96091 7.39387 6.1673" width="7.39387pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M536 404C536 423 520 448 491 448C445 448 398 404 308 283L286 338C255 416 242 448 217 448C182 448 138 402 92 341L111 321C149 368 169 378 178 378C188 378 198 363 214 320L254 212C185 117 138 65 107 65C98 65 85 69 82 75C79 82 73 86 65 86C44 86 23 60 23 39C23 7 44 -12 71 -12C119 -12 168 33 265 177L306 61C321 17 347 -12 373 -12C413 -12 465 33 507 96L491 119C459 84 432 60 413 60C395 60 378 92 358 148L321 250C341 279 369 310 389 332C417 363 439 382 456 382C466 382 475 376 481 368C486 361 492 358 496 358C513 358 536 381 536 404Z" id="g113-121"></path></g></svg> with respect to the commensurate fractional-order <span class="nowrap"><svg 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Complexity

fig8

Figure 8

Figure 8: Analysis of a No Equilibrium Linear Resistive-Capacitive-Inductance Shunted Junction Model, Dynamics, Synchronization, and Application to Digital Cryptography in Its Fractional-Order Form 

Figure 8 | Analysis of a No Equilibrium Linear Resistive-Capacitive-Inductance Shunted Junction Model, Dynamics, Synchronization, and Application to Digital Cryptography in Its Fractional-Order Form 