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Complexity
Volume 2017, Article ID 9696342, 12 pages
https://doi.org/10.1155/2017/9696342
Research Article

A Novel Graphical Technique for Combinational Logic Representation and Optimization

1Chair of Embedded Intelligence for Health Care and Wellbeing, University of Augsburg, Augsburg, Germany
2Group on Language, Audio & Music (GLAM), Imperial College London, London, UK

Correspondence should be addressed to Vedhas Pandit; moc.liamg@sahdev

Received 5 June 2017; Revised 11 October 2017; Accepted 14 November 2017; Published 31 December 2017

Academic Editor: Michele Scarpiniti

Copyright © 2017 Vedhas Pandit and Björn Schuller. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

We present a new technique for defining, analysing, and simplifying digital functions, through hand-calculations, easily demonstrable therefore in the classrooms. It can be extended to represent discrete systems beyond the Boolean logic. The method is graphical in nature and provides complete ‘‘implementation-free” description of the logical functions, similar to binary decision diagrams (BDDs) and Karnaugh-maps (K-maps). Transforming a function into the proposed representations (also the inverse) is a very intuitive process, easy enough that a person can hand-calculate these transformations. The algorithmic nature allows for its computing-based implementations. Because the proposed technique effectively transforms a function into a scatter plot, it is possible to represent multiple functions simultaneously. Usability of the method, therefore, is constrained neither by the number of inputs of the function nor by its outputs in theory. This, being a new paradigm, offers a lot of scope for further research. Here, we put forward a few of the strategies invented so far for using the proposed representation for simplifying the logic functions. Finally, we present extensions of the method: one that extends its applicability to multivalued discrete systems beyond Boolean functions and the other that represents the variants in terms of the coordinate system in use.

1. Introduction and Literature Overview

Combinational logic optimization is one of the first steps when designing any digital circuit. This practice helps chip designer save on number of transistors, chip area, and helps reduce logic delays and power requirements. It is no surprise therefore that many efforts have been made to develop fully functional, interactive programs for the industry even in the 80s, such as MIS [1] and SOCRATES [2] and the field has only grown ever since with the advent of many companies competing in this domain. In this section, we discuss various logic optimization methods. Advantages and drawbacks associated with each of these popular methods, especially the ones that offer graphical representation of a function or are simple enough for humans to hand-calculate, is the primary focus of this section. In view of the listed advantages and drawbacks, characteristic features of an ideal methodology are then presented.

A Karnaugh-map (K-map) [3, 4] is a graphical technique for combinational logic optimization, which offers a very intuitive way to hand-calculate the proposed graphical representation of a Boolean function and its reduction. Using different colour schemes, multiple output functions involving the same inputs can be represented on a single K-map. However, it is only ideal for a function where the number of inputs is less than five. To represent functions involving more than four variables, one of the proposed implementations splits the graph into subgraphs—each subgraph representing only four variables at a time [5]. Another extension of the K-maps does not require splitting the graph into smaller units to represent functions with more than four variables, but some of the variable inversions can no longer remain adjacent to each other [6]—like in the case of K-maps for four inputs.

A binary decision diagram (BDD) [710] is also a graphical method that is easy enough to implement and visualise. BDDs are often put to use as a data structure to both represent the Boolean functions and to perform the operations efficiently. Unlike K-maps, usability of this approach is not constrained by the number of inputs. Optimization is primarily about choosing the correct ordering of input variables and about reducing the number of “nodes” by merging equivalent nodes and by removing redundant ones. Diagram complexity depends a lot on the ordering of the input variables and the respectively applied decomposition type [7, 11], and it is not always easy to devise the correct order by mere visual inspection. This however, to a limited extent, is also a downside of the graphical approaches presented in this paper. As for BDDs, moreover, one cannot translate a given graphical representation back to its Boolean expression just by a quick visual skimming through—it is imperative to trace the entire paths starting from the output nodes back to the first input in order.

Typed decision graphs (TDGs) [12] offer reduction of BDDs into a graph with a lot fewer nodes and connections. The advantages and drawbacks of the method are therefore mostly similar to those of BDDs, including dependence of the size/complexity of the representation on the ordering of the variables. Also closely related to BDDs are graphical techniques called “implicit graph based method” [1315] and signal transition graphs (STGs) [16].

The Quine–McCluskey algorithm [1719] (or method of prime implicants) is functionally identical to Karnaugh mapping and is a deterministic way to check that the minimal form of a Boolean function has been reached. The tabular form makes it more efficient for use in computer algorithms, but, not being graphical, it is not as simple or as intuitive as Karnaugh-maps for use by the designer himself/herself. Petrick’s method (the branch-and-bound method) [20] is a technique for determining all minimum sum-of-products solutions from a prime implicant chart and could be looked upon as an extension to the Quine–McCluskey algorithm. The process gets tedious for a human for a large number of inputs and does not scale well on computers likewise. The Espresso algorithm [21] uses a radically different approach by applying heuristics, manipulating the “cubes” representing the product terms in the ON-, DC-, and OFF-covers iteratively, instead of expanding the minterms. Recently, a new paradigm has been proposed called “Majority-Inverter Graph” [22], which is a directed acyclic graph consisting of three-input majority nodes and direct/negated edges.

Keeping classroom education of Boolean functions at the focus, several methodologies [2327] that are mostly nongraphical and can best be demonstrated with systems with only a limited number of inputs have been proposed, in addition to more generalised software implementations [2832] not directly useful for demonstrating the concepts through easy hand-calculations. Karnaugh-maps—due to the method’s graphical nature—continue to be used as the first method to explain the optimization process in the switching theory textbooks [33] still today.

In the context of the comparison of the methods noted so far, we propose that the following are the desired characteristics of an ideal logic representation methodology:(i)It is not constrained by the number of inputs or outputs and can in theory handle an infinite number of inputs and outputs. That is to say, multiple output functions can be represented simultaneously.(ii)The optimization process should be intuitive; ideally visual inspection should be enough to establish input-output relationship. Or it should be based on a paradigm that is intuitive enough for a human to simply hand-calculate. Graphical methods like K-maps do offer that advantage.(iii)If it is graphical, an equivalent numerical method should exist, which can effectively be used as a data structure to optimally represent combinational logic through conventional programming.(iv)Translating a Boolean equation into the graphical representation (or vice versa) is a simple process.(v)Ordering of variables should play no role in the complexity of the representation.

The proposed technique satisfies all of the desired characteristics listed, except the very last one. Ordering of variables contributes to the ease with which a human can optimize a function without using any computing resources.

2. Definitions

(i)The logical operators/symbols “”, “+”, “”, “”, and “” denote the logical negation, OR, AND, XOR, and XNOR operations, respectively.(ii)The symbols “” and “” denote the logical AND and OR operations of the variables in iteration, respectively.(iii) is a set of inputs to the combinational logic block under consideration.(iv) denotes an empty set.(v)SOP = sum of products.(vi)POS = product of sums.

3. Proposed Technique (Pandit-Plot)

Every Boolean equation is represented by a scatter plot in two dimensions. In effect, in its simplest version, corresponding to four quadrants, four Boolean expressions can simultaneously be represented and optimized on a single plane. By using different markers, one for each function, multiple logic functions may be represented in a single plane and subsequently reduced.

3.1. Coordinate System and Input Correspondence

Every integer coordinate “” corresponds to an input combination such thatOne axis (say -axis) represents a condition where the designated inputs are all (also called or logic level ), while the other represents a case where those inputs are all (also called or logic level ). There is, therefore, a one-to-one correspondence between the set of all of combinations of the inputs and the set of points on the plane with integer coordinates. With such a representation system in place, every point on the plot with integer coordinates signifies a single product (in a SOP representation) or a single sum (in a POS representation). As an example, for a system with three inputs (), the template of the plot that is restricted to the first quadrant () will be as shown in Figure 1.

Figure 1: Pandit-Plot (for ) with redundant data-points.

Throughout the discussion henceforth, we only consider the template in the first quadrant. The templates in four quadrants are symmetric to each other, with - and -axes and the “” and “” lines as the axes of symmetry. We observe that, in the scatter plot from Figure 1, certain data-points have been marked distinctively using the filled circles. These will be called “redundant” input combinations—for the reasons that will be explained in Section 3.3.

3.2. Representing an Input Combination

Representation of the combinational function “” in graphical form may be done for “” either in POS or in SOP form; the choice lies with the logic designer/user of the plot.

To represent a function in SOP form, every constituent product term is separated into two products, one containing exclusively the direct inputs and the other only the negated inputs. The overall product is represented by a point , where, for example, the -coordinate corresponds to the set of input combinations coming only from the direct inputs, while the -coordinate corresponds to the set of input combinations from only the negated inputs, using (1). The absence of inputs implies that the corresponding coordinate is 0.

As an example, let us consider the following sum of products:represented by points and , shown in Figure 2.(i)For the first product “” to be , both and need to be . Therefore, the -coordinate = , as per (1). Because there are no negated inputs in the first product, no needs to be for to be . Therefore, the -coordinate is 0. The product “” is, therefore, represented by point .(ii)Similarly, for the product “” to be , both and need to be . Therefore, the -coordinate = , as per (1). Also, needs to be for function to be . Therefore, the -coordinate . The product “” is, therefore, represented by point .

Figure 2: Pandit-Plot for .

Points and will be called “data-points” as they summarise the function by transforming it into numerical data, corresponding to the chosen coordinate system.

Similarly, for a POS-based representation, we look for () logic outputs to mark the points transforming every sum in the expression.

Every Boolean function can therefore be represented by only two parameters alone in this way, namely, the coordinates of the representative points, irrespective of the number of inputs. This is a huge data compression in itself, where instead of storing the entire truth table, or even all of the combinations for which the output is either T or F (whichever count is less), we can simply represent a function with a few data-points. The system can further be optimized to remove extraneous information as will be explained in Sections 3.3, 3.5, and 3.6.

3.3. Existence of Redundant Data-Points

It can easily be observed that there exist points on the plot with integer coordinates that correspond to a Boolean product or a Boolean sum that can never occur in a reduced SOP or a reduced POS expression, respectively.

As an example, point corresponds to the () product in SOP which evaluates to , and the same point corresponds to the sum in POS which evaluates to . These input combinations do not have any effect on the final expression evaluation, as the output corresponding to these input combinations is preknown and therefore redundant to be included as part of any Boolean expression (e.g., ). We therefore discard such input cases and term these as “redundant points” in the discussions below, while the rest will be called “valid” points, except the origin, which falls into neither of the two categories, representing simply the trivial case of the output being independent of the inputs.

3.4. Generation of the Template

To translate any logic function to this plot, the first step is to build the necessary template or the canvas with all the input redundancies indicated (Figure 1). Such a template may be generated by exploiting patterns for which the redundancies appear (Algorithm 1).

Algorithm 1: Redundant set generation for Pandit-Plot.

For example, we note the following for a system with inputs:(i)The - and -axes extend from to .(ii)The points on the line are redundant points.(iii)All of the upper diagonal elements are redundant points.(iv)Redundant points because of the input’s logic level extend along both the and directions skipping every other point, that is, skipping the odd integer coordinates. The redundant points associated with input are therefore of the form , where are integers.(v)Alternatively, the template may be generated using cellular automata rules on a brick-wall-like automata template as devised in Figure 3 (in contrast to the typical cellular automata template as used in Conway’s game of life [34, 35]—where the borders of the individual cells coincide). This gives rise to the Sierpinski triangle [36, 37] pattern, as desired. The captions for the individual blocks indicate the coordinates of the points that the blocks represent.

Figure 3: Template generation from 2 different kinds of rules, signifying its relation to the Sierpinski triangle/fractals and the cellular automata.
3.5. Logic Laws

The logic optimization process is visual, intuitive, and simple—just as for Karnaugh-maps. It may alternatively be easily implemented using a computer program by understanding the strategies in place numerically. The basic idea of optimization is to get rid of excess of information by inspecting the scatter plot and bring the data-points as close to the axes as possible. There exist patterns that need to be utilised to effectively carry out this “reduction.” These patterns need to be formulated into a compilation of “logic laws.” A few examples of a logic law or an optimization strategy follow.

Theorem 1 (-integer-multiple hypotenuse rule). If two of the data-points are vertices of an upright right angled isosceles triangle with its equal sides having length =    and if the third vertex is not to the right of any of those two data-points, then the two data-points could effectively be represented by that third vertex alone, so long as the third vertex is not a redundant point.

Proof. Let data-points be and , such that and and ,  , without loss of generalisation.
Because none of the three points, , , and , is a redundant point and because , it follows thatwhere is set of suffixes corresponding to inputs associated with coordinate “.
Similarly, it follows thatTherefore, the point represents both the direct and negated inputs corresponding to the point , along with the input . Similarly, the point represents both the direct and negated inputs corresponding to the point , along with the input . The two points, and , therefore, effectively represent the inputs corresponding to the point and, in addition, either the direct or the negated version of the input .
Therefore, in SOP form,and, in POS form,where   function associated with point .
Thus, as per (5) and (6), this rule is simply a manifestation of the two well-known equalities    and    for the template we present here—where and are, respectively, the product terms and the summation terms consisting of variables excluding .

As an illustration, if the plot in Figure 4 represents a Boolean function in SOP form with the points and as its “data-points,” then per the definitions earlierThis is because point translates to “,” while point represents “.

Figure 4: Diagonal optimization for SOP.

Per the law proposed, points and are represented together by point alone, since the right angled triangle is an isosceles triangle with its congruent sides having length , ).

We find here that the hypothesis is true, since

If the scatter plot in Figure 4 were to correspond to a POS representation, then the plot would have been represented asEffectively,

In either case, points and are together represented by alone.

Theorem 2 (symmetry about “” line). Two “valid” points symmetric about the “” line in an SOP plot can be effectively represented by a newly defined logical operation represented by operator , whereTwo “valid” points symmetric about the “” line in a POS plot can be effectively represented by a newly defined logical operation represented by operator , where

Proof. Two points symmetric about the “” line will be of the forms and . It follows that the set of direct inputs corresponding to the point    is the same as the set of negated inputs that are represented by point and vice versa .
Because points and are not redundant points, it follows that .
Therefore, for SOP,Similarly, for POS,

For a system with just two inputs, the “” operator represents simply an “XOR” () operation, while the “” operator represents an “XNOR” () operation. The “NAND-only” implementation of “” operation is shown in Figure 5. This newly defined logic gate can then be optimized for given fan-in and fan-out values as necessary to be used as a building block in the subsequent logic design.

Figure 5: “NAND-only” implementation of the newly defined logical operations “ and ” that are essentially (XOR) and (XNOR) operations, respectively, for a two-input system.
3.6. Process of Optimization

While there is much scope for further research in this area for effective algorithm development in terms of logic optimization, including the ones targeted to novel topologies such as the ones involving IMPLY gates alone, for example (instead of SOP/POS forms presented here, effectively implemented using “NAND alone” and “NOR alone” topologies, resp.), one of the most likely logic flows for such optimization is presented next.

Steps involved in this example algorithm are as follows:(i)“Generate” the template and plot the function.(ii)“Expand” the expression to include every possible product in SOP form (every possible sum for a POS form).(iii)“Reduce” the expression using logic laws.(iv)“Repeat” the above two steps in iteration until no further reduction is possible, as illustrated in Figure 6.

Figure 6: Process of optimization; the steps in order are illustrated.

As an example, let , and let the representation form chosen be SOP-based as well. ultimately gets reduced to as shown in Figure 6.(1)Generate: plot the product terms (Figure 6(a)).(2)Expand: plot points relevant to each of the current data-points (Figure 6(b)). Here, is expanded to include points wherever .(3)Reduce: reduce the expression using logic laws. If a new data-point, replacing one or some of the original data-points, is obtained through this process and if this data point cannot be further reduced, then it is noted and kept for the next iteration. (We note an example of such data-point with a label “NEW” in Figure 6(c).)(4)Repeat: repeat steps and until no new replacement data-point closer to the origin can be obtained (Figure 6(d)).

Similar to the Karnaugh-maps, the “do not care” input combinations could be exploited for logic reduction [3, 38].

3.7. As a Data Structure

Because the individual Boolean terms are represented by only two coordinates (irrespective of the number of inputs), any combinational logic may be represented by two parameters alone. This can be viewed as a conversion of a graphical scheme to an equivalent nongraphical numerical scheme, to be handled by computing systems efficiently. The two coordinates may be stored in the memory as a single unit.

Because one can represent any logic expression through a set of coordinates alone, we now investigate the number of bits required to store each of the numbered coordinates. While a proposed template for inputs consists of points (including the origin), the number of valid coordinates is only . This is because a variable can manifest itself in an input combination in its original form () or as a negated version () or it could simply be absent. Thus, there are three possibilities for every input . The number of valid points is, therefore, (excluding the origin indicative of a trivial case where the output is independent of all of the inputs under consideration). Both the total number of points () in a template and the number of valid points () grow exponentially with . The ratio of the number of bits thus required (with and without considering the redundant points) = which varies between and and eventually converges to for large . As an example, for , , and , while, for , , and . Memory savings, thus, grow with if we effectively take into account the redundancies in the template.

However, in comparison to K-maps ( cells for an -input system), our proposed method requires a much higher number of points (, if we consider only the valid input combinations, excluding the origin). This is because the K-maps do not take into account all of the input combinations, but only the ones where each of the inputs manifests itself by its presence in its original or in its negated form (thus, possibilities). In the proposed method, we explicitly take into account also the reduced input combinations where some of the inputs are absent.

3.8. Possible Extensions and Further Research Scope

(i)Beyond SOP/POS paradigms: more patterns and the resulting optimization strategies need to be investigated in different logic gate methodologies, for example, SOP (“AND-OR”, which is “NAND-only”), POS (“OR-AND”, which is “NOR-only”), and “IMPLY-only” realisations.(ii)Multilevel logic: the concept could be extended to three dimensions to represent a ternary logic system, where both inputs and outputs can have three possible logic levels . The resulting representation is, thus, in the form of a “logic lattice” instead of the two-dimensional grid presented here, where the third dimension would serve a dual purpose. First, it represents a condition where all the inputs are logical level “2” (just as and represented states “1” and “0,” resp.). Secondly, the -axis may also represent an output logic level within such a “logic slice.” As an example, output level-1 may correspond to a point with integer coordinates, level-0 may correspond to a point just beneath this point, and level-2 just above (Figure 7).(iii)Alternate coordinate systems: every data-point symbolises a huge degree of information, but with only two or three parameters (coordinates). Because this information need not necessarily come about using a Cartesian coordinate system alone, one can choose to alternatively employ some other coordinate system and look for patterns and laws for optimization within such schemes. For example, a 2D polar system may be used, where the to transformation is governed by the equations , , and . Note that remains in the range irrespective of the number of inputs (Figure 8). The logic laws for such alternate coordinate systems—where every coordinate of interest follows the equation ,  —can be devised by recognising the inherent patterns, which remains an open problem with further scope for research.

Figure 7: Ternary logic representation (). The point or represents the input condition, where all inputs corresponding to -coordinate = 1, all inputs corresponding to -coordinate = 0, and all inputs corresponding to -coordinate = 2.
Figure 8: Cartesian coordinate system converted into polar system, where , , and . Filled circles indicate the “redundant points.”
3.9. Implications to Other Fields of Study

One can use the template to establish three algebraic equalities, as will be discussed in detail in this section. The method, in general, is useful for alternative representation and processing of data whenever there is representation of information (i.e., encoding or decoding) in the form of distinct or discrete states. The basic representation strategy can therefore be extended to represent and optimize operations on qubits [39] or to represent codon tables [40, 41] or design digital synthetic gene circuits [42]. Using the template used in the method proposed, we have derived the following three equalities in relation to . The method gives practical evidence of the equalities invented and presented next.

Theorem 3. or, in other words,

Theorem 4.

Theorem 5. As a consequence,Let us first establish that the equalities being discussed are true, using induction.

Proof. For Theorem 3, we observe that the equalities presented in (15) or (16) are true for and .For ,For ,Now, say, for some ,Therefore,For , therefore,Therefore, if the statement is true for , then the statement is true for (). Because the statement is true for and , it is true for every and .

Proof. For Theorem 4 similarly, we observe that the equality presented in (17) is true for :Now, say, for some ,For , therefore,Because the statement is true for , it is true for every and .

In the context of the template for the method proposed, the two theorems can be proven graphically by simply counting the number of valid and redundant points, via different formulations. If for all , we know the following:(i) = = total number of points.(ii) total number of “valid” data-points, including the origin.( Every input can manifest itself in the input combination represented by (), either in its original form (input combination represented by th -coordinate) or as a negated input (input combination represented by the -coordinate) or may not manifest itself at all.)(iii) = total number of redundant points.( Total number of points = total number of “valid” points including the origin + total number of “redundant” points).

Proof. To establish equality presented in the Theorem 3, we use the formulation of as presented in Figure 9. From Figure 9, it is evident thatThe exponent of 3 translates to a multiplier that represents the frequency of occurrence of the constituent triangle of that specific size in the template.

Figure 9: Total number of “redundant points”/the points in the darkened region, by counting the number of points in constituent triangles separately.

Proof. Alternately, Theorem 4 can be proven using a recursive formula for , as obtained from Figure 10.

Figure 10: Total number of “redundant points”/the points in the darkened region, by deriving a recursive formula for . Thus, .

This method can be used in classrooms to quickly hand-calculate an optimized form of the logic function using a ruler and a compass alone (Figure 11).

Figure 11: A compass and a ruler (marked with units) can be effectively used to quickly find the points that can be merged together to generate a more optimized logic representation using the logic laws proposed earlier (Section 3.5).

4. Conclusion

A novel graphical technique for digital logic representation and optimization has been proposed, which makes optimization algorithm much more instinctive and easy. Multiple equations can be optimized simultaneously using the template presented. One can, theoretically, therefore optimize simultaneously multiple combinational logic circuits with any number of inputs or outputs. We propose a data structure transformation that can compress a truth table into a few parameters. The approach and the fundamentals involved are likely to generate many novel solutions applicable to other disciplines. A new paradigm is being proposed, which opens up new avenues for research in terms of new methodologies and pattern identification towards better logic reduction tailored to different implementation topologies such as SOP (“AND-OR”/“NAND-only”), POS (“OR-AND”/“NOR-only”), and “IMPLY-only” realisations or the newer methodologies such as “reconfigurable asynchronous logic automata (RALA)” [43] and the search for most suited template for each in terms of the coordinate system of choice and the template generation rules.

Our proposed technique currently establishes a one-to-one mapping between all of the possible variable combinations and the corresponding output states—representing the absence and presence of every variable (in its original and the negated form) for each of the variable combinations. One possible future research direction is to investigate the relationship between the proposed technique herein and other representation techniques—such as QMDDs which, too, rely on quadrants and one-to-one mappings and which rather extend way beyond the proposed technique to represent transformation matrices featuring complex entries useful for logic involving qubits. Further research may also be targeted towards multilevel discrete systems beyond Boolean algebra and reversible [44, 45] and hazard-free logic synthesis [9].

Conflicts of Interest

The authors declare that there are no conflicts of interest regarding the publication of this paper.

References

  1. R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, “MIS: A Multiple-Level Logic Optimization System,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 6, no. 6, pp. 1062–1081, 1987. View at Publisher · View at Google Scholar · View at Scopus
  2. A. J. De Geus and W. Cohen, “A Rule-Based System for Optimizing Combinational Logic,” IEEE Design Test of Computers, vol. 2, no. 4, pp. 22–32, 1985. View at Publisher · View at Google Scholar · View at Scopus
  3. M. Karnaugh, “The map method for synthesis of combinational logic circuits,” Transactions of the American Institute of Electrical Engineers, Part I: Communication and Electronics, vol. 72, no. 5, pp. 593–599, 1953. View at Google Scholar
  4. M. E. Holder, “A modified karnaugh map technique,” IEEE Transactions on Education, vol. 48, no. 1, pp. 206-207, 2005. View at Publisher · View at Google Scholar · View at Scopus
  5. J. Cavanagh, Computer Arithmetic and Verilog HDL Fundamentals, CRC Press, 2009. View at Publisher · View at Google Scholar
  6. Z. Kohavi and N. K. Jha, Switching and finite automata theory, Cambridge University Press, 2009.
  7. C. Y. Lee, “Representation of switching circuits by binary-decision programs,” Bell Labs Technical Journal, vol. 38, pp. 985–999, 1959. View at Publisher · View at Google Scholar · View at MathSciNet · View at Scopus
  8. S. B. Akers, “Binary decision diagrams,” IEEE Transactions on Computers, vol. 27, no. 6, pp. 509–516, 1978. View at Publisher · View at Google Scholar · View at Scopus
  9. B. Lin and S. Devadas, “Synthesis of Hazard-Free Multilevel Logic Under Multiple-Input Changes from Binary Decision Diagrams,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 8, pp. 974–985, 1995. View at Publisher · View at Google Scholar · View at Scopus
  10. C. Yang and M. Ciesielski, “BDS: A BDD-based logic optimization system,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 7, pp. 866–876, 2002. View at Publisher · View at Google Scholar · View at Scopus
  11. R. E. Bryant, “Graph-based algorithms for boolean function manipulation,” IEEE Transactions on Computers, vol. C-35, no. 8, pp. 677–691, 1986. View at Publisher · View at Google Scholar · View at Scopus
  12. L. Mauborgne, “Abstract interpretation using typed decision graphs,” Science of Computer Programming, vol. 31, no. 1, pp. 91–112, 1998. View at Publisher · View at Google Scholar · View at Scopus
  13. O. Coudert and J. C. Madre, “A new implicit graph-based prime and essential prime computation technique,” in Proceedings of the Proc. International Symp. Information Sciences, Fukuoka, Japan, 1992.
  14. O. Coudert and J. C. Madre, “A New Graph Based Prime Computation Technique,” in Logic Synthesis and Optimization, pp. 33–57, Springer, Boston, MA, USA, 1993. View at Publisher · View at Google Scholar
  15. O. Coudert, J. C. Madre, H. Fraisse, and H. Touati, “Implicit prime cover computation: An overview,” in Proceedings of the in Proc. Synthesis and Simulation Meeting and International Interchange (SASIMI), Nara, Japan, 1993.
  16. J. Gu and R. Puri, “Asynchronous circuit synthesis with Boolean satisfiability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 8, pp. 961–973, 1995. View at Publisher · View at Google Scholar · View at Scopus
  17. W. V. Quine, “The problem of simplifying truth functions,” The American Mathematical Monthly, vol. 59, pp. 521–531, 1952. View at Publisher · View at Google Scholar · View at MathSciNet
  18. W. V. Quine, “A way to simplify truth functions,” The American Mathematical Monthly, vol. 62, pp. 627–631, 1955. View at Publisher · View at Google Scholar · View at MathSciNet
  19. J. McCluskey, “Minimization of Boolean functions,” Bell Labs Technical Journal, vol. 35, pp. 1417–1444, 1956. View at Publisher · View at Google Scholar · View at MathSciNet · View at Scopus
  20. S. Petrick, “A direct determination of the irredundant forms of a boolean function from the set of prime implicants,” Tech. Rep., Air Force Cambridge Research Center, 1956. View at Google Scholar
  21. R. L. Rudell, “Multiple-Valued Logic Minimization for PLA Synthesis,” Defense Technical Information Center, 1986. View at Publisher · View at Google Scholar
  22. L. Amaru, P.-E. Gaillardon, and G. De Micheli, “Majority-Inverter Graph: A New Paradigm for Logic Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 5, pp. 806–819, 2016. View at Publisher · View at Google Scholar · View at Scopus
  23. D. C. Fielder, “Classroom Reduction of Boolean Functions,” IEEE Transactions on Education, vol. 9, no. 4, pp. 202–205, 1966. View at Publisher · View at Google Scholar · View at Scopus
  24. B. C. H. Turton, “Extending Quine-McCluskey for exclusive-or logic synthesis,” IEEE Transactions on Education, vol. 39, no. 1, pp. 81–85, 1996. View at Publisher · View at Google Scholar · View at Scopus
  25. R. Benzer and V. Rozga, “The Design and Application of a Minority Logic Gate-A Senior Project,” IEEE Transactions on Education, vol. 10, no. 3, pp. 141–146, 1967. View at Publisher · View at Google Scholar · View at Scopus
  26. N. R. Bell, “A Map Method for the Teaching of the Fundamental Concepts of Compound-Input Logic Circuits,” IEEE Transactions on Education, vol. 11, no. 3, pp. 173–177, 1968. View at Publisher · View at Google Scholar · View at Scopus
  27. R. F. Tinder, “Multilevel Logic Minimization Using K-map XOR Patterns,” IEEE Transactions on Education, vol. 38, no. 4, pp. 370–375, 1995. View at Publisher · View at Google Scholar · View at Scopus
  28. B. D. Carroll and I. Chen, “ABAL—A Language for Boolean Function Representation and Manipulation,” IEEE Transactions on Education, vol. 20, no. 1, pp. 70–72, 1977. View at Publisher · View at Google Scholar · View at Scopus
  29. C. E. Klock, F. R. Schneider, M. V. N. Gomes, D. S. Moura, R. P. Ribas, and A. I. Reis, “KARMA: A didactic tool for two-level logic synthesis,” in Proceedings of the MSE 2007: 2007 IEEE International Conference on Microelectronic Systems Education: Educating Systems Designers for the Global Economy and a Secure World, pp. 59-60, San Diego, CA, USA, June 2007. View at Publisher · View at Google Scholar · View at Scopus
  30. V. P. Correia and A. I. Reis, “A tutorial tool for switch logic,” in Proceedings of the International Conference on Microelectronic Systems Education, MSE 2001, pp. 28-29, Las Vegas, NV, USA, June 2001. View at Publisher · View at Google Scholar · View at Scopus
  31. Z. Stanisavljevic, V. Pavlovic, B. Nikolic, and J. Djordjevic, “SDLDS-system for digital logic design and simulation,” IEEE Transactions on Education, vol. 56, no. 2, pp. 235–245, 2013. View at Publisher · View at Google Scholar · View at Scopus
  32. P. Corsini and L. Rizzo, “SSCSSC: A Tool for the Teaching of Digital Circuits,” IEEE Transactions on Education, vol. 34, no. 1, pp. 70–75, 1991. View at Publisher · View at Google Scholar · View at Scopus
  33. G. J. Klir and M. A. Marin, “New considerations in teaching switching theory,” IEEE Transactions on Education, vol. 12, no. 4, pp. 257–261, 1969. View at Publisher · View at Google Scholar · View at Scopus
  34. M. Gardner, “Mathematical games: The fantastic combinations of John Conway's new solitaire game "life",” Scientific American, vol. 223, no. 4, pp. 120–123, 1970. View at Publisher · View at Google Scholar
  35. S. Wolfram, “Cellular automata as models of complexity,” Nature, vol. 311, no. 5985, pp. 419–424, 1984. View at Publisher · View at Google Scholar · View at Scopus
  36. M. Sierpinski, “Sur une courbe dont tout point est un point de ramification,” Compte Rendus hebdomadaires des séance de lÁcadémie des Science de Paris, vol. 160, pp. 302–305, 1915. View at Google Scholar
  37. J.-P. Allouche and J. Shallit, Automatic Sequences: Theory, Applications, Generalizations, Cambridge University Press, 2003.
  38. K. A. Bartlett, R. K. Brayton, G. D. Hachtel et al., “Multilevel Logic Minimization Using Implicit Don't Cares,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 6, pp. 723–740, 1988. View at Publisher · View at Google Scholar · View at Scopus
  39. P. Niemann, R. Wille, D. M. Miller, M. A. Thornton, and R. Drechsler, “QMDDs: Efficient Quantum Function Representation and Manipulation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 1, pp. 86–99, 2016. View at Publisher · View at Google Scholar · View at Scopus
  40. D. Searls and M. Noordewier, “Pattern-matching search of DNA sequences using logic grammars,” in Proceedings of the Seventh IEEE Conference on Artificial Intelligence Application, pp. 3–9, Miami Beach, FL, USA, 1991. View at Publisher · View at Google Scholar
  41. C. R. Woese, “Order in the genetic code.,” Proceedings of the National Acadamy of Sciences of the United States of America, vol. 54, no. 1, pp. 71–75, 1965. View at Publisher · View at Google Scholar
  42. M. A. Marchisio and J. Stelling, “Automatic design of digital synthetic gene circuits,” PLoS Computational Biology, vol. 7, no. 2, Article ID e1001083, 2011. View at Publisher · View at Google Scholar · View at Scopus
  43. N. Gershenfeld, D. Dalrymple, K. Chen et al., “Reconfigurable asynchronous logic automata: (RALA),” in Proceedings of the 37th Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL'10, vol. 45, pp. 1–6, Madrid, Spain, January 2010. View at Publisher · View at Google Scholar · View at Scopus
  44. V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes, “Synthesis of reversible logic circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 6, pp. 710–722, 2003. View at Publisher · View at Google Scholar · View at Scopus
  45. P. Gupta, A. Agrawal, and N. K. Jha, “An algorithm for synthesis of reversible logic circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 11, pp. 2317–2329, 2006. View at Publisher · View at Google Scholar · View at Scopus