Research Article
Hybrid Network-on-Chip: An Application-Aware Framework for Big Data
| | Buffered NoC/bufferless NoC |
| Topology | 2D mesh, 8 × 8 size | Routing algorithm | X-Y routing, flit-by-flit | Routing latency | 2 cycles | Core | Out-of-order, 16 MSHR, 128 instruction windows size | L1 I-cache and D-cache: 32 KB, 64 B line-size, 2-way, LRU, 2-cycle latency | L1 cache | Private | L2 cache | Per-block interleaving shared, distributed, 64 B line-size, perfect |
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