Complexity

Volume 2018, Article ID 8405978, 21 pages

https://doi.org/10.1155/2018/8405978

## Exact Analysis and Physical Realization of the 6-Lobe Chua Corsage Memristor

Division of Electronics and Information Engineering and Intelligent Robots Research Center (IRRC), Chonbuk National University, Jeonju, Jeonbuk 567-54896, Republic of Korea

Correspondence should be addressed to Hyongsuk Kim; rk.ca.unbj@miksh

Received 20 April 2018; Accepted 11 July 2018; Published 1 November 2018

Academic Editor: Viet-Thanh Pham

Copyright © 2018 Zubaer I. Mannan et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

A novel generic memristor, dubbed the *6-lobe Chua corsage memristor*, is proposed with its nonlinear dynamical analysis and physical realization. The proposed corsage memristor contains *four* asymptotically stable equilibrium points on its complex and diversified dynamic routes which reveals a *4-state nonlinear memory device*. The higher degree of versatility of its dynamic routes reveal that the proposed memristor has a variety of dynamic paths in response to different initial conditions and exhibits a highly nonlinear *contiguous* DC *V*-*I* curve. The DC *V*-*I* curve of the proposed memristor is endowed with an explicit *analytical parametric representation*. Moreover, the derived *three formulas*, exponential trajectories of state , time period , and minimum pulse amplitude , are required to analyze the movement of the state trajectories on the piecewise linear (PWL) dynamic route map (DRM) of the corsage memristor. These *formulas* are universal, that is, applicable to any *PWL DRM curves* for any *DC* or *pulse input* and with any *number of segments*. Nonlinear dynamics and circuit and system theoretic approach are employed to explain the *asymptotic quad-stable behavior* of the proposed corsage memristor and to *design* a *novel real memristor emulator* using *off-the-shelf* circuit components.

#### 1. Introduction

Memristor, the acronym of memory resistor, is one of the most propitious elements in the emerging memory sector due to its exclusive attributes under DC or AC excitations, as well as its miniature nanoscale physical dimension. Extensive research is ongoing on memristors and the memristive system after the seminal paper published by *hp* in 2008 [1]. Memristor, the fourth basic circuit element, was postulated by Chua [2] and later generalized to a broader class of dynamical devices which exhibit interesting and valuable circuit-theoretic properties [3].

Recently, several researchers investigated the multistate phenomena in generic and extended memristors [4–7]. This important research direction could lead to another stage of technical innovation in the memristor area. The principle of the multistate memristor can be explained using the nonlinear dynamics theory as well as circuit and system theoretic concepts [4–6]. For example, the locally active generic Chua corsage memristor exhibits an asymptotical stability via the supercritical Hopf bifurcation [8–9]. Once an initial state is set, the state alters following its nonlinear dynamic route. The state changing is repeated until the state reaches a particular state which is termed as an “attractor.” In this type of memristors, the state space contains various attractors and each attractor has its own basin of attraction [10]. When inputs or noises are applied at a stable equilibrium state of the generic corsage memristor, the equilibrium state is moved by the amount of time integral of the inputs. However, unless the state moves beyond the boundary of current basin of attraction, the state returns back to its original equilibrium state (attractor) [8, 9]. Therefore, it can become a robust memory device. Since a part of the previous programming history of the corsage memristor is lost in this procedure, the phenomenon is known as “local fading memory” in bistable and multistate memory devices [4].

Another feature of this type of multistate corsage memristor is the alteration of the stable equilibrium states. In this case, a sufficiently large amplitude with short pulse width or a minimum pulse amplitude with lengthy pulse width is applied across the memristor to switch the state from one stable equilibrium state to another stable state by converging into the basin of a new stable attractor. In this way, the equilibrium state of a multistate corsage memristor is changed to a new stable state where the resistances or conductances of each stable equilibrium state are distinguishably different from each other [7]. The alteration of the stable equilibrium states of corsage memristors is determined by the function of its input and initial condition, and henceforth, the corsage memristors exhibit multistability and eventually can be used as multistate memory devices.

In this paper, we demonstrate a novel quad-stable generic memristor, dubbed the *6-lobe Chua corsage memristor*. The dynamic routes of the 6-lobe corsage memristor have *four* asymptotically stable equilibrium points and *three* unstable equilibrium points at the DC input voltage *V* = 0 V. The *four* asymptotically stable equilibrium points of the proposed memristor define the corresponding four distinct resistance levels and can be used to develop a multibit-per-cell memory device similar to the unidirectional spin Hall magnetoresistance [11]. The multistable memory states are distinguishable by resistance levels in accordance to stable equilibrium points where the memory states can be defined with a pair of bits. To ease the demonstration of the switching kinetics of multistable memory states of the proposed memristor, we derived *three universal formulas* regarding the exponential state , the time period , and the minimum pulse amplitude .

In addition to the theoretical insights, we have designed and built a real emulator circuit of the proposed corsage memristor. For the physical realization of the piecewise linear 6-lobe Chua corsage memristor, we use the Graetz bridge [12] circuit in parallel with an *active and locally active* resistor [5]. Concepts from circuit and system theory, and techniques from nonlinear dynamics theory, are employed in this paper to elucidate the key mechanisms underlying the emergence of switching strategies of quad-stable memory.

The rest of the paper is organized as follows: the 6-lobe corsage memristor is designed and introduced in Section 2. The parametric representation and DC *V*-*I* curve are analyzed in Section 3. The switching kinetics and the physical implementation of the proposed corsage memristor are described in Sections 4 and 5, respectively, followed by the concluding remarks in Section 6.

#### 2. 6-Lobe Chua Corsage Memristor Model

The *6-lobe Chua corsage memristor* is an extension of the 1st-order locally active Chua corsage memristor [8]. It is a *piecewise linear* (*PWL*) memristor whose state-dependent Ohm’s law and state equation are as follows:
where
and
where
and , , and denote the memristor state, current, and voltage, respectively. In practice, is a scaling constant chosen to fit the intrinsic memductance scale of the memristor. In this paper, we choose so that the current of the 6-lobe Chua corsage memristor can be measured in *milliamperes* (*mA*) [7].

##### 2.1. Frequency-Dependent Pinched Hysteresis Loops

The frequency-dependent pinched hysteresis loops of a device, when driven by any periodic input current or voltage source with a zero DC component, are a signature of a memristor or memristive system [13]. The 6-lobe Chua corsage memristor defined in (1), (2), (3), and (4) exhibits frequency-dependent pinched hysteresis loops when it is driven by a sinusoidal input signal where , as shown in Figure 1. The input voltage and the corresponding memristor current are shown in the upper-right side of Figure 1(a), and the memristor state and memductance are shown in the lower-right side of Figure 1(a), whereas the left side of Figure 1(a) shows the memristive circuit diagram with AC excitation. The frequency-dependent pinched hysteresis loops are shown in Figure 1(b) for frequencies , , , and . The lobe area of the pinched hysteresis loops shrinks as the frequency increases and tends to a straight line for as shown in Figure 1(b) [14]*.* It follows that the proposed corsage memristor is a generic memristor [15].