Memory Circuit Elements: Complexity, Complex Systems, and Applications
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Zubaer I. Mannan, Changju Yang, Shyam P. Adhikari, Hyongsuk Kim, "Exact Analysis and Physical Realization of the 6Lobe Chua Corsage Memristor", Complexity, vol. 2018, Article ID 8405978, 21 pages, 2018. https://doi.org/10.1155/2018/8405978
Exact Analysis and Physical Realization of the 6Lobe Chua Corsage Memristor
Abstract
A novel generic memristor, dubbed the 6lobe Chua corsage memristor, is proposed with its nonlinear dynamical analysis and physical realization. The proposed corsage memristor contains four asymptotically stable equilibrium points on its complex and diversified dynamic routes which reveals a 4state nonlinear memory device. The higher degree of versatility of its dynamic routes reveal that the proposed memristor has a variety of dynamic paths in response to different initial conditions and exhibits a highly nonlinear contiguous DC VI curve. The DC VI curve of the proposed memristor is endowed with an explicit analytical parametric representation. Moreover, the derived three formulas, exponential trajectories of state , time period , and minimum pulse amplitude , are required to analyze the movement of the state trajectories on the piecewise linear (PWL) dynamic route map (DRM) of the corsage memristor. These formulas are universal, that is, applicable to any PWL DRM curves for any DC or pulse input and with any number of segments. Nonlinear dynamics and circuit and system theoretic approach are employed to explain the asymptotic quadstable behavior of the proposed corsage memristor and to design a novel real memristor emulator using offtheshelf circuit components.
1. Introduction
Memristor, the acronym of memory resistor, is one of the most propitious elements in the emerging memory sector due to its exclusive attributes under DC or AC excitations, as well as its miniature nanoscale physical dimension. Extensive research is ongoing on memristors and the memristive system after the seminal paper published by hp in 2008 [1]. Memristor, the fourth basic circuit element, was postulated by Chua [2] and later generalized to a broader class of dynamical devices which exhibit interesting and valuable circuittheoretic properties [3].
Recently, several researchers investigated the multistate phenomena in generic and extended memristors [4–7]. This important research direction could lead to another stage of technical innovation in the memristor area. The principle of the multistate memristor can be explained using the nonlinear dynamics theory as well as circuit and system theoretic concepts [4–6]. For example, the locally active generic Chua corsage memristor exhibits an asymptotical stability via the supercritical Hopf bifurcation [8–9]. Once an initial state is set, the state alters following its nonlinear dynamic route. The state changing is repeated until the state reaches a particular state which is termed as an “attractor.” In this type of memristors, the state space contains various attractors and each attractor has its own basin of attraction [10]. When inputs or noises are applied at a stable equilibrium state of the generic corsage memristor, the equilibrium state is moved by the amount of time integral of the inputs. However, unless the state moves beyond the boundary of current basin of attraction, the state returns back to its original equilibrium state (attractor) [8, 9]. Therefore, it can become a robust memory device. Since a part of the previous programming history of the corsage memristor is lost in this procedure, the phenomenon is known as “local fading memory” in bistable and multistate memory devices [4].
Another feature of this type of multistate corsage memristor is the alteration of the stable equilibrium states. In this case, a sufficiently large amplitude with short pulse width or a minimum pulse amplitude with lengthy pulse width is applied across the memristor to switch the state from one stable equilibrium state to another stable state by converging into the basin of a new stable attractor. In this way, the equilibrium state of a multistate corsage memristor is changed to a new stable state where the resistances or conductances of each stable equilibrium state are distinguishably different from each other [7]. The alteration of the stable equilibrium states of corsage memristors is determined by the function of its input and initial condition, and henceforth, the corsage memristors exhibit multistability and eventually can be used as multistate memory devices.
In this paper, we demonstrate a novel quadstable generic memristor, dubbed the 6lobe Chua corsage memristor. The dynamic routes of the 6lobe corsage memristor have four asymptotically stable equilibrium points and three unstable equilibrium points at the DC input voltage V = 0 V. The four asymptotically stable equilibrium points of the proposed memristor define the corresponding four distinct resistance levels and can be used to develop a multibitpercell memory device similar to the unidirectional spin Hall magnetoresistance [11]. The multistable memory states are distinguishable by resistance levels in accordance to stable equilibrium points where the memory states can be defined with a pair of bits. To ease the demonstration of the switching kinetics of multistable memory states of the proposed memristor, we derived three universal formulas regarding the exponential state , the time period , and the minimum pulse amplitude .
In addition to the theoretical insights, we have designed and built a real emulator circuit of the proposed corsage memristor. For the physical realization of the piecewise linear 6lobe Chua corsage memristor, we use the Graetz bridge [12] circuit in parallel with an active and locally active resistor [5]. Concepts from circuit and system theory, and techniques from nonlinear dynamics theory, are employed in this paper to elucidate the key mechanisms underlying the emergence of switching strategies of quadstable memory.
The rest of the paper is organized as follows: the 6lobe corsage memristor is designed and introduced in Section 2. The parametric representation and DC VI curve are analyzed in Section 3. The switching kinetics and the physical implementation of the proposed corsage memristor are described in Sections 4 and 5, respectively, followed by the concluding remarks in Section 6.
2. 6Lobe Chua Corsage Memristor Model
The 6lobe Chua corsage memristor is an extension of the 1storder locally active Chua corsage memristor [8]. It is a piecewise linear (PWL) memristor whose statedependent Ohm’s law and state equation are as follows: where and where and , , and denote the memristor state, current, and voltage, respectively. In practice, is a scaling constant chosen to fit the intrinsic memductance scale of the memristor. In this paper, we choose so that the current of the 6lobe Chua corsage memristor can be measured in milliamperes (mA) [7].
2.1. FrequencyDependent Pinched Hysteresis Loops
The frequencydependent pinched hysteresis loops of a device, when driven by any periodic input current or voltage source with a zero DC component, are a signature of a memristor or memristive system [13]. The 6lobe Chua corsage memristor defined in (1), (2), (3), and (4) exhibits frequencydependent pinched hysteresis loops when it is driven by a sinusoidal input signal where , as shown in Figure 1. The input voltage and the corresponding memristor current are shown in the upperright side of Figure 1(a), and the memristor state and memductance are shown in the lowerright side of Figure 1(a), whereas the left side of Figure 1(a) shows the memristive circuit diagram with AC excitation. The frequencydependent pinched hysteresis loops are shown in Figure 1(b) for frequencies , , , and . The lobe area of the pinched hysteresis loops shrinks as the frequency increases and tends to a straight line for as shown in Figure 1(b) [14]. It follows that the proposed corsage memristor is a generic memristor [15].
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2.2. Dynamic Routes with Their Phase Portrait
The dynamic route of a nonlinear system prescribes the dynamics of nonlinear differential equations [14]. The dynamic route of the shortcircuited (v = 0 V), namely, the poweroffplot (POP), 6lobe Chua corsage memristor is shown in Figure 2 where (5) is used to plot the loci of .
The arrowheads in Figure 2 indicate the direction of motion of the state variable from any initial state .
Figure 2 shows that for any initial state on the upper half of the POP, where , the state variable must move to the right as increases with time, depicted by the purple arrowheads pointing to the right in Figure 2. On the contrary, for any initial state on the lower half of the POP, where , the state variable decreases with time and must move to the left, depicted by the black arrowheads pointing to the left in Figure 2. In the theory of nonlinear dynamics [16], the stationary points where or intersects the xaxis; are known as equilibrium points. Figure 2 shows that intersects the xaxis at seven points, namely, (Q_{1}), (Q_{2}), (Q_{3}), (Q_{4}), (Q_{5}), (Q_{6}), and (Q_{7}). The equilibrium points Q_{1}, Q_{3}, Q_{5}, and Q_{7} are stable whereas Q_{2}, Q_{4}, and Q_{6} are unstable equilibrium points because the state variable diverges away from Q_{2}, Q_{4}, and Q_{6}. Moreover, the equilibrium points Q_{1}, Q_{3}, Q_{5}, and Q_{7} in Figure 2 are stable as the corresponding eigenvalues of those equilibrium points are negative real numbers whereas Q_{2}, Q_{4}, and Q_{6} are unstable as the eigenvalues are positive [17].
Figure 2 shows that for any initial state , where , the unstable equilibrium points Q_{2}, Q_{4}, and Q_{6} converge to stable equilibrium points Q_{3}, Q_{5}, and Q_{7}, respectively, to their right as shown with purple arrowheads. In contrast, for any initial state , Q_{2}, Q_{4}, and Q_{6} converge to stable equilibrium points Q_{1}, Q_{3}, and Q_{5}, respectively, to their left as shown with black arrowheads.
The phase portrait of stable equilibrium states Q_{1}, Q_{3}, Q_{5}, and Q_{7} is shown in Figure 3 where the dotted straight lines represent the separatrices between two stable equilibrium states and pass through the unstable equilibrium points Q_{2}, Q_{4}, and Q_{6}, respectively. Similar to Figure 2, Figure 3 also shows that for any , the trajectories of converge to Q_{3}, Q_{5}, and Q_{7}, respectively, as shown with purple arrowheads. Conversely, for , converges to Q_{1}, Q_{3}, and Q_{5}, respectively, as shown with black arrowheads.
The dynamic routes in Figure 2 and the phase portrait in Figure 3 illustrate that the proposed memristor can be used as a 4state or multibitpercell (2bit) memory device at v = 0 V.
The more stable equilibrium states of the 6lobe corsage memristor increases the memory efficiency per device 50% and 25% compared to 2lobe and 4lobe corsage memristors, respectively, and eventually enhance the capability to represent a desired function more closely than 2lobe or 4lobe corsage memristors.
3. Parametric Representation and the DC VI Curve
In mathematics, parametric representation of an object is a collection of parametric equations which are used to express the coordinates of the points that make up a geometric object [18] where those parametric equations are defined by a group of quantities based on a function of one or more independent variables [19].
3.1. Parametric Representation
The parametric representation of the 6lobe Chua corsage memristor can be derived by equating state (3) to zero () and solving for the following equilibrium points (6) for each DC input voltage , at the DC equilibrium state :
The DC voltage of the proposed corsage memristor is given explicitly by
The parametric representation of the DC current of the 6lobe corsage memristor can be derived by substituting given by (7) for in (1) with G_{0} = 10^{−6}, namely,
The parametric representations of the proposed corsage memristor are shown in Figure 4 where Figures 4(a) and 4(b) show the loci of the parametric representation of and , respectively. The loci of the parametrically represented are shown in Figure 4(c).
(a)
(b)
(c)
For convenience of readers, several points of the parametric representation of and of the 6lobe Chua corsage memristor over the range are listed in Table 1.

3.2. DC VI Plot
A circuittheoretic approach is used to derive the DC VI loci of the voltagecontrolled 6lobe Chua corsage memristor. Each DC value of voltage V and current I is computed using the following steps: (1)For each value of listed in Table 1, we calculate all equilibria , , of the proposed memristor using state (3) where (2)Then we determine the DC current of the memristor corresponding to each equilibrium point , : (3)Finally, we draw the DC VI curve by plotting the coordinates (V, I) on the VI plane for each value of .
The DC VI loci of the 6lobe corsage memristor is shown in Figure 5 over the input voltage range −10 V ≤ V ≤ 10 V where the solid curves correspond to stable equilibrium states and the dash curves correspond to unstable equilibrium states. Since the DC VI curve contains six contiguous lobes, henceforth call it the “six lobe corsage VI curve.” The seven different colored DC VI branches in Figure 5 represent the equilibrium points of the corresponding colors in Figure 3. At , the state variables are (red DC VI curve Q_{1}), (fluorescent green DC VI curve Q_{2}), (blue DC VI curve Q_{3}), (magenta DC VI curve Q_{4}), (cyan DC VI curve Q_{5}), (brown DC VI curve Q_{6}), and (green DC VI curve Q_{7}). As the values of the state variable of each DC VI branch at the origin are different, their slopes (i.e., conductances ) at the origin are also different according to (2), as tabulated in the upperleft inset of Figure 5. The tabulated upperleft inset shows that the red DC VI curve represents the lower conductance state (higher resistance state) whereas the green DC VI curve represents the higher conductance state (lower resistance state). Moreover, the lowerright inset of Figure 5 shows a zoomed portion of the red DC VI curve over the range −5 V ≤ V ≤ 2 V. The zoomed red DC VI curve contains a negativeslope region over the voltage range −3 V < V < −1 V which affirms that the proposed corsage memristor is locally active over the −3 V < V < −1 V range as for DC input voltage () [8]. The locally active negative slope region of the 6lobe Chua corsage memristor is significant in circuit theory as it might give rise to complexity through which complex phenomenon and information processing might emerge [20, 21].
One of the most important features of the 6lobe corsage memristor is the contiguousness of its DC VI curve which is different from many other published nonlinear DC VI curves which exhibit several disconnected branches [14].
Another impressive feature is that the parametric representation and the DC VI curve of the proposed corsage memristor has an explicit analytical equation, which rarely happens.
4. Switching Strategies of Memory States
The poweroffplot in Figure 2 shows that the 6lobe Chua corsage memristor can be used as a 4state or 2bit memory device at . Conceptually, the simplest way to switch the memory states of the 6lobe corsage memristor is to apply a square pulse with an appropriate pulse amplitude and pulse width . For a successful switching between the memory states of the proposed corsage memristor, the square pulse should have a minimum pulse width for an appropriate pulse amplitude, . Any square pulse with less than the minimum pulse width results in switching failure.
The switching kinetics of the 6lobe Chua corsage memristor can be represented through its dynamic route map (DRM). The solution of each straightline segment of the dynamic route map of our corsage memristor is an exponential function where the complete solution x(t) is made of a sequence of the exponential waveforms, joined at the various breakpoints in the dynamic routes. In this paper, we derived the following universal exponential state variable formula related to a straightline segment around an equilibrium point of the piecewise linear DRM (detailed derivation of , , and are provided in the supplementary document (available here).): where represents the sign value of the straightline slope, and is the initial time of the segment whereas represents the initial state at . The universal formula of the time, , required for the trajectory of to move from any initial point to the end of the straightline segment is also derived as follows:
The appropriate pulse amplitude is computed by replacing in (11) and substituting the value of from (13) to (11) where the resultant equation is shown as follows: where and represent, respectively, the immediate before equilibrium point and the initial state of the resultant memory state .
The derived universal formulas in (11), (12), (13), and (14) are applicable for any piecewise linear DRM curve of any number of segments and any DC or pulse input . Such exponential analytical solutions can be derived from no nonlinear functions other than the PWL functions.
The dynamic route map (DRM) in Figure 6(a) shows an application of successful switching for an appropriate pulse amplitude and pulse width where the 6lobe corsage memristor switches from highresistance (low conductance) state Q_{1} to lowresistance (high conductance) state Q_{5}. To switch from Q_{1} to Q_{5}, we choose the pulse amplitude which satisfies the condition . To compute the appropriate pulse width , we choose the final state (with input V_{A}) for a square pulse by satisfying the condition , as shown in Figure 6(a). For , the proposed corsage memristor fails to switch from memory state Q_{1} to Q_{5} and converges to memory state Q_{3}. However, pulse width is equal to the time required for the trajectories to move from x_{1}(t_{01}) to and can be computed by summing the time needed for each individual straightline segment to reach the terminal points and express as
(a)
(b)
The total time period required to move from memory state Q_{1} to Q_{5} is expressed as as shown in Figure 6. The sequence of exponential x(t) obtained from (11) is shown as follows: and by inserting the initial states, equilibrium points, and time period for the trajectories to move from initial states to final states, the x(t) can be expressed as follows:
The memory state switching from Q_{1} to Q_{5} in Figure 6(a) shows that the applied square pulse with V_{A} = 5.5 V is equivalent to translating the red curve upwards by 5.5 units, as shown by the blue curve. The dynamic route starting from Q_{1} (), at , would jump abruptly from Q_{1} on the red curve to a point directly above Q_{1} on the blue curve (yellow circle) at (shown with the upward green arrow) as the pulse input increases from 0 V to 5.5 V. Since the blue curve is located above the xaxis (where ) over the range of interest, its motion can only move to the right, until time . When the square pulse returns to zero at , the point (shown with the green circle) on the blue curve reverts back abruptly to the point on the red curve (shown with the light cyan circle followed by the downward green arrowhead), whereupon the dynamics must continue to move along the dynamic route indicated by the black arrowheads, until it converges to the lowresistance memory state Q_{5} ().
The exponential trajectories of the related with the individual piecewise linear segments are shown in Figure 6(b). Observe from Figure 6(b) that the total time period () needed for the trajectories to reach Q_{5} from Q_{1} is the summation of all the time periods needed for an individual trajectory to propagate through the piecewise linear segments which is .
To switch back from the lowresistance (high conductance) state Q_{5} to the highresistance (low conductance) state Q_{1} of our corsage memristor, we simply applied a negative voltage pulse with amplitude V_{A} = −5.5 V and pulse width where is computed using (15). The dynamic route and the state trajectories of switching back kinetics from memory states Q_{5} to Q_{1} is shown in Figures 7(a) and 7(b), respectively. In Figure 7(a), at , the state variable and the slope at that linear segment for which the state variable must move to the right and eventually converge to the equilibrium memory state Q_{1} (). The similar phenomenon with exponential trajectories of is shown in Figure 7(b) where the decreases as the time increases and converges to where is regarded as the Q_{1} memory state. To switch back from Q_{5} to Q_{1}, the total time is needed as shown in Figure 7(b).
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(b)
The pulse amplitude and the pulse width play a crucial role in the switching kinetics of the memory states of the 6lobe Chua corsage memristor. An inappropriate pulse amplitude or pulse width may result in switching failures. To choose the appropriate pulse amplitude , we already provided (14) whereas we illustrate the inappropriate pulse width scenario in Figure 8. In Figure 8, we provide the same pulse amplitude to switch from memory state Q_{1} to Q_{5} with a different pulse width . Observe from Figure 8(b) that the exponential trajectories are converging to memory state Q_{3} () rather than converging to memory state Q_{5} (). The reason behind such switching failure is the pulse width as at and the state variable which lies in the lefthand side of Q_{4} (), as shown in Figure 8(a). According to Section 2.2, any point that lies in the left side of Q_{4} (x = 25) follows the dynamic route (as shown with the black arrowhead in Figure 2) and converges to equilibrium state Q_{3}, and in this case, the state variable follows the same route and converges to Q_{3} (x = 15) as x_{Δw}(t = Δw) < Q_{4}.
(a)
(b)
For convenience of the readers, we plotted the hyperbolic relationship between the pulse amplitude versus the pulse width of the switching memory states between Q_{1} and Q_{5} of our 6lobe corsage memristor as shown in Figure 9.
5. Physical Realization of the 6Lobe Chua Corsage Memristor
For physical realization of the 6lobe Chua corsage memristor, we modified the circuit in Figure 1(a) with the switching kinetics closer to the behavioral attributes of our 7segment PWL hypothetical memristor which is shown in Figure 10. The novel circuit consists of the cascade between a passive nonlinearresistive twoport and a dynamic firstorder oneport [5]. The passive nonlinearresistive twoport is composed of parallel connected Graetz bridges [12] with opposite diode directions whereas the dynamic firstorder oneport is made up of a CR parallel circuit.
The active and locally active resistor R_{0} in Figure 10 should exhibit the contiguous six breakpoints on its DC VI curve similar to the 6lobe Chua corsage memristor. To design the nonlinear resistor R_{0}, we applied the circuittheoretic analysis on an opamp circuit [22] to obtain the desired DC VI breakpoints at specific voltages. According to [22], the drivingpoint characteristic of a single positive and negative feedback opamp circuit provides two breakpoints on its piecewise linear DC VI curve. To obtain a sixbreakpoint piecewise linear DC VI curve, we combine three opamp circuits in parallel as shown in Figure 11. The current coming out from the parallel opamp circuit in Figure 11 provides a piecewise linear DC VI curve with six breakpoints when plotted in the VI plane.
The active and locally active twoport (marked with the black box) in Figure 11 consists of three opamp circuits (marked with red, blue, and magenta boxes) in parallel. The circuit parameters and the components of the three opamp circuit in Figure 11 are similar for each box except the negative feedback resistances (R_{41}, R_{42}, and R_{43}) which determine the effective saturation voltage of an individual opamp circuit. The saturation voltage along with the negative feedback resistance play a key role to achieve the VI breakpoints at specified voltages such as , , and . The opamp circuits in Figure 11 also contain a positive feedback path where the difficulty arises with the drivingpoint and transfer function. To resolve this problem, we replace the opamp circuit in the red box (in Figure 11) by its three ideal models, such as the “Linear region,” “+Saturation region,” and “−Saturation region” as shown in Figures 12(a)–12(c), respectively.
(a)
(b)
(c)
The Linear region of the opamp circuit in Figure 12(a) shows that the potential difference between the noninverting terminal () and the inverting terminal () is zero, so the differential voltage and eventually inverting terminal voltage,
The following relation between output voltage and inverting terminal voltage can be computed by the voltage divider rule where and henceforth
Pedagogically, in the linear region, the relation between the saturation voltage (±) and output voltage is as follows: for which, in the Linear region, the relation between the input voltage and saturation voltage (±) is
The loop provides linear region current as
For the +Saturation region shown in Figure 12(b), the relation between the output voltage and the saturation voltage is as follows: and the differential voltage , so that , and eventually the relationship between input voltage and saturation voltage is
The current for the +Saturation region is computed as follows:
For the −Saturation region shown in Figure 12(c), the relation between the output voltage and the saturation voltage is and , so that , and henceforth, the relationship between the input voltage and saturation voltage is and the −Saturation region current is computed as
The current flowing out of the opamp circuit in Figure 11 is computed by adding all currents (, , and ):
Plotting the output voltage and input current with respect to the input voltage of the opamp circuit with positive and negative feedback paths over the specified ranges of all the three regions provides a piecewise linear curve as shown in Figure 13(a). The opamp circuit enclosed in the red box in Figure 11 exhibits two breakpoints at V = ±7 V with circuit parameters R_{33} = 1K, R_{43} = 1K, R_{63} = 100K, R_{73} = 1K, and E_{sat} = 14 V over the input voltage range −14 V ≤ V ≤ 14 V. The mathematical simulation results shown in Figure 13 shows that the linear region of the opamp circuit lies in the range −7 V ≤ V ≤ 7 V (as ) whereas the positive and negative saturation regions lie at and , respectively. Moreover, the output voltage at the positive and negative saturation regions are and , respectively, and in the linear region, v_{03} increases proportionately to the input voltage . However, the current of the opamp circuit increases linearly in the saturation region and decreases in an inversely proportional manner to the input voltage in the linear region.
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(b)
(c)
Similarly, following the circuittheoretic concepts mentioned above, the input currents and of the opamp circuits in Figure 11 are computed as and
The loci of versus and versus and versus and versus are shown in Figures 13(b) and 13(c), respectively.
The total current flowing out of the 3 parallel connected opamp circuits in Figure 11 is equal to the summation of the three currents (, , and ) of the individual opamp circuits and computed as
The sixbreakpoint VI curve of nonlinear resistor is shown in Figure 14. Mathematical simulation results of current and the equivalent nonlinear resistance are shown in Figure 14(a) with the parameters (the measured resistor values of circuit implementation are used in mathematical and SPICE simulations) , , , , , , and . The plots of the current and the active and locally active resistance obtained by SPICE simulation and the actual circuit implementation are shown in Figures 14(b) and 14(c), respectively.
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The mathematical simulation presented in Figure 14(a) shows that the VI curve and the resistance value of the nonlinear resistor has six breakpoints at V = ±6.99 V, ±4.95 V, and ±2.82 V. The slope of is different between these breakpoints and hence defines different memory states. Similar to the mathematical model, the plots of the VI curve and the nonlinear resistance obtained by SPICE simulation and the circuit implementation also have six breakpoints at V = ±6.9 V, ±4.89 V, and ±2.77 V and V = ±5.74 V, ±4.05 V, and ±2.15 V, respectively. The insets in Figures 14(a)–14(c) show the zoomed figure of near the origin and show that at input voltage .
The nonlinear resistance waveform obtained from the SPICE modelling in Figure 14(b) shows that the is constant at resistance 147.47 Ω for an input voltage range −2.77 V < V < 2.77 V, except for a tiny interval at the origin (V = 0 V). However, for 2.77 V < V < 4.89 V and 4.89 V < V < 6.9 V, the increases linearly from 147.47 Ω to 216.07 Ω and from 216.07 Ω to 336.10 Ω, respectively, whereas for V > 6.9 V, increases almost linearly. Due to the linear increment of with a constant slope over the abovementioned voltage range, it can be acclaimed that the real 6lobe corsage memristor emulator contains four different memory states, namely, R_{01}, R_{02}, R_{03}, and R_{04} where R_{01} = (R_{0} = 147.47 Ω), R_{02} = (147.47 Ω < R_{0} ≤ 216.07 Ω), R_{03} = (216.07 Ω < R_{0} ≤ 336.10 Ω), and R_{04} = (R_{0}> 336.10 Ω).
Similar to the SPICE model, the mathematical and the circuit implementation plots of also contains the four different memory states as shown in Figures 14(a) and 14(b), respectively. The fluctuation of R_{0} at the −2.16 V < V < 2.16 V voltage range in Figure 14(c) is negligibly small and can be regarded as R_{0} = 137 Ω. The fluctuation was induced due to computational difficulties at V = 0 V in the oscilloscope. Although the resistance of the mathematical model of the 6lobe corsage memristor and the real emulator are quantitatively different, they are also qualitatively identical.
The breakpoints of the VI curve of the nonlinear resistor in mathematical simulation, shown in Figure 14(a) and the SPICE simulation shown in Figure 14(b), are slightly different. This deviation happens due to the nonideal circuit components of the SPICE module. Moreover, the VI curve breakpoints of measured from the circuit implementation is further deviated from the mathematical and SPICE simulation. The reason behind such deviation is the nonideal characteristic of the opamp circuit as well as the noise induced from the DC power supply and the oscilloscope probe. Another reason for such deviation is the used opamp’s rated saturation voltage () which is slightly less than the mathematical and SPICE saturation voltage .
Although the breakpoints of the DC VI curve in Figure 5 and the breakpoints of Figure 14 are quantitatively different, they are qualitatively similar. In this artifact, one of our primary motives is to show that the basic method explained in [4, 5] and [14] can be used to convert the DC VI curve of any real nonlinear resistor into a memristor. We prove this analogy by analyzing the parallel connected opamp circuit in Figure 11 which has the capabilities to emulate the attributes of the 6lobe Chua corsage memristor as it exhibits a 7segment PWL DC VI curve as shown in Figure 14.
The SPICE simulation of switching of memory states of the real 6lobe Chua corsage memristor emulator (in Figure 10) is shown in Figure 15. Figure 15(a) shows the example of successful switching between the memory states R_{01} and R_{03}. To switch from R_{01} to R_{03}, a pulse input with a pulse width is applied across our real emulator circuit in Figure 10. Observe from Figure 15(a) that the resistance at , and it gradually increases during the pulse period and saturated at and remained there although the input voltage become zero for . The saturated resistance lies over the memory state R_{03} = (216.07 Ω < R_{0} ≤ 336.10 Ω) which confirms the successful switching from memory state R_{01} to R_{03} for an input pulse and . However, to fit the resistance scale, we truncated the part of the in Figure 15(a) as that part is insignificant because at , immediately rises from to .
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(b)
In this paper, we also demonstrate the switching failure scenario of the real 6lobe Chua corsage memristor as shown in Figure 15(b). In Figure 15(b), a pulse input with a pulse width is applied across our real emulator. The nonlinear resistance is saturated at and remained there as the time increases although the voltage becomes for . The resultant resistance lies over the memory state R_{02} = (147.47 Ω < R_{0} ≤ 216.07 Ω) which confirms the failure of switching as our intention is to switch from memory state R_{01} to R_{03} for an input pulse and , but we converge on memory state R_{02}.
The switching failure scenario gives us the insights that the emulator circuit of our proposed corsage memristor is also dependent on the appropriate pulse amplitude and the pulse width like its mathematical model. To illustrate the relationship of pulse amplitude and the pulse width in our real emulator circuit, we plot the pulse amplitude V_{A} versus pulse width Δw curve as shown in Figure 16. The hyperbolic relationship in Figure 16 shows that the maximum pulse amplitude V_{A} requires less pulse width to switch from one memory state to another state whereas the minimum pulse amplitude requires maximum pulse width.
6. Conclusion
The recent interest in inherently nonlinear memristor devices is bringing to a new life to the theory of nonlinear circuits and systems. In this paper, we design and build a highly nonlinear novel device, namely, the 6lobe Chua corsage memristor, and its real emulator circuit using the nonlinear circuit theory. The proposed generic memristor can be used as a multistate, specifically 4state, memory device with an increased efficiency of 50% compared to the 2lobe and bistable extended memristor whereas the efficiency of the proposed memristor increased by 25% compared to the 4lobe corsage memristor. Moreover, due to the presence of more equilibrium points compared to the 2lobe or 4lobe corsage memristors, the proposed corsage memristor exhibits a higher variety of dynamic routes in response to different initial conditions which enhance the capability to represent a desired function more closely than 2lobe or 4lobe corsage memristors. Due to the diversified dynamic routes and the enhancement in stable memory states, the proposed corsage memristor is more versatile and effective than its predecessor 2lobe and 4lobe corsage memristors. Moreover, the diversified dynamic routes reveal a contiguous highly nonlinear DC VI curve with six distinct contiguous hysteresis lobes, unlike the most published highly nonlinear disconnected DC VI curves. Furthermore, the universal formulas, derived in Section 4, ease the demonstration of the switching kinetics of the 6lobe corsage memristor and assist to switch the memory states preciously with an appropriate pulse amplitude and pulse width in accordance to an initial condition . The universal formulas are applicable to any device which exhibits a PWL dynamic route map with any number of segments for any DC or pulse input. Following the introduction of a purely mathematical memristor model with quad stability (2bit memory system) at DC and pulse input, this paper elucidates the mechanisms behind the emergence of the first real emulated 6lobe Chua corsage memristor using offtheshelf elements. Nonlinear system theoretic concepts were applied to the model of the twoport memristive element to gain a deep insight into the quadstable characteristic of its dynamics where the quantitative attributes of the real emulator might not be similar to the mathematical model but they are qualitatively same.
Data Availability
The data used to support the findings of this study are available from the first author or corresponding author upon request.
Conflicts of Interest
The authors declare that they have no conflicts of interest.
Acknowledgments
The authors would like to thank Professor Leon Chua for his wonderful assistance for revising the manuscript and technical advice. This work was supported in part by the National Research Foundation of Korea (NRF) grant funded by the Korean Government (2016R1A2B4015514), the “Cooperative Research Program for Agriculture Science and Technology Development (Project no. PJ0120642016),” the Rural Development Administration, Republic of Korea, and the US Air Force Office of Scientific Research under Grant no. FA95501810016.
Supplementary Materials
Finding of universal formulas. Figure 1: dynamic routes of the switching kinetics of the 6lobe Chua corsage memristor. The two magentacolor vertical line segments indicate an instantaneous jump between the red and the blue piecewiselinear plots in the dynamic route map. Figure 2: movement of the exponential trajectories of x(t) with respect to time t. (Supplementary Materials)
References
 D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, “The missing memristor found,” Nature, vol. 453, no. 7191, pp. 80–83, 2008. View at: Publisher Site  Google Scholar
 L. Chua, “Memristorthe missing circuit element,” IEEE Transactions on Circuit Theory, vol. 18, no. 5, pp. 507–519, 1971. View at: Publisher Site  Google Scholar
 L. O. Chua and S. M. Kang, “Memristive devices and systems,” Proceedings of the IEEE, vol. 64, no. 2, pp. 209–223, 1976. View at: Publisher Site  Google Scholar
 A. Ascoli, R. Tetzlaff, and L. O. Chua, “The first ever real bistable memristors—part I: theoretical insights on local fading memory,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 12, pp. 1091–1095, 2016. View at: Publisher Site  Google Scholar
 A. Ascoli, R. Tetzlaff, and L. O. Chua, “The first ever real bistable memristors—part II: design and analysis of a local fading memory system,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 12, pp. 1096–1100, 2016. View at: Publisher Site  Google Scholar
 S. Stathopoulos, A. Khiat, M. Trapatseli et al., “Multibit memory operation of metaloxide bilayer memristors,” Scientific Reports, vol. 7, no. 1, article 17532, 2017. View at: Publisher Site  Google Scholar
 Z. I. Mannan, C. Yang, and H. Kim, “Oscillation with 4lobe Chua corsage memristor,” IEEE Circuits and Systems Magazine, vol. 18, no. 2, pp. 14–27, 2018. View at: Publisher Site  Google Scholar
 Z. I. Mannan, H. Choi, and H. Kim, “Chua corsage memristor oscillator via Hopf bifurcation,” International Journal of Bifurcation and Chaos, vol. 26, no. 4, 2016. View at: Publisher Site  Google Scholar
 Z. I. Mannan, H. Choi, V. Rajamani, H. Kim, and L. Chua, “Chua corsage memristor: phase portraits, basin of attraction, and coexisting pinched hysteresis loops,” International Journal of Bifurcation and Chaos, vol. 27, no. 3, 2017. View at: Publisher Site  Google Scholar
 S. H. Strogatz, “Phase plane,” in Nonlinear Dynamics and Chaos, pp. 145–150, AddisonWesley Publishing Co., MA, USA, 2nd edition, 1994, ch. 6, sec 6.1–6.3. View at: Google Scholar
 C. O. Avci, M. Mann, A. J. Tan, P. Gambardella, and G. S. D. Beach, “A multistate memory device based on the unidirectional spin Hall magnetoresistance,” Applied Physics Letters, vol. 110, no. 20, 2017. View at: Publisher Site  Google Scholar
 R. Strzelecki and G. S. Zinoviev, “Overview of power electronics converters and controls,” in Power Electronics in Smart Electrical Energy Networks, Power Systems, pp. 55–105, SpringerVerlag Limited, London, 2008. View at: Publisher Site  Google Scholar
 S. P. Adhikari, M. P. Sah, H. Kim, and L. O. Chua, “Three fingerprints of memristor,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 11, pp. 3008–3021, 2013. View at: Publisher Site  Google Scholar
 L. Chua, “If it’s pinched it’s a memristor,” Semiconductor Science and Technology, vol. 29, no. 10, 2014. View at: Publisher Site  Google Scholar
 L. Chua, “Everything you wish to know about memristors but are afraid to ask,” Radioengineering, vol. 24, no. 2, pp. 319–368, 2015. View at: Publisher Site  Google Scholar
 L. O. Chua, Introduction to Nonlinear Network Theory, McGrawHill, New York, USA, 1969.
 J. J. E. Slotine and W. Li, “Advance stability theory,” in Applied Nonlinear Control, PrenticeHall, Inc., New Jersey, 1991. View at: Google Scholar
 G. B. Thomas and R. L. Finney, Calculus and Analytic Geometry, AddisonWesley Publishing Co., MA, USA, 5th edition, 1979.
 Stover and E. W. Weisstein, “Parametric equations,” MathWorldA Wolfram Web Resource, 2017, http://mathworld.wolfram.com/ParametricEquations.html. View at: Google Scholar
 K. Mainzer and L. Chua, Local Activity Principle: the Cause of Complexity and Symmetry Breaking, Imperial College Press, UK, 2013. View at: Publisher Site
 M. P. Sah, Z. I. Mannan, H. Kim, and L. Chua, “Oscillator made of only one memristor and one battery,” International Journal of Bifurcation and Chaos, vol. 25, no. 3, 2015. View at: Publisher Site  Google Scholar
 L. O. Chua, C. A. Desoer, and E. A. Kuh, “Operationalamplifier circuits,” in Linear and Nonlinear Circuits McGraw Hill, pp. 187–212, New York, USA, 1985, ch. 4, sec. 3. View at: Google Scholar
Copyright
Copyright © 2018 Zubaer I. Mannan et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.