Fully Integrated Chen Chaotic Oscillation System

Ouyang, Ziyi; Jin, Jie; Yu, Fei; Chen, Long; Ding, Lei

doi:https://doi.org/10.1155/2022/8613090

Discrete Dynamics in Nature and Society

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Abstract Introduction Conclusion Data Availability Conflicts of Interest Acknowledgments References Copyright Related Articles

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Modelling, Control Methods and Applications of Chaotic Oscillators

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Research Article | Open Access

Volume 2022 | Article ID 8613090 | https://doi.org/10.1155/2022/8613090

Fully Integrated Chen Chaotic Oscillation System

Ziyi Ouyang,¹Jie Jin,^1,2Fei Yu ,³Long Chen,¹and Lei Ding²

Academic Editor: Sundarapandian Vaidyanathan

Received21 Dec 2021

Revised10 Jan 2022

Accepted25 Jan 2022

Published15 Feb 2022

Abstract

A fully integrated Chen chaotic oscillation system using operational amplifiers (OAs) and multipliers is designed and verified in this paper. Unlike the conventional breadboard-based Chen chaotic system using off-the-shelf discrete components, the fully integrated Chen chaotic oscillation circuit presented in this paper is realized using GlobalFoundries’ 0.18 μm CMOS 1P6M process, and all the circuit components are integrated in a chip. The fully integrated Chen chaotic oscillation system is verified using Cadence IC Design Tools, and the post-layout simulation results indicate that the presented integrated Chen chaotic oscillation system only consumes 148 mW from ± 2.5 V supply voltage, and its chip area is 6.15 mm²_.

1. Introduction

With the development of nonlinear systems, the research on chaos and chaotic neural networks has grown rapidly in recent years [1–10]. However, the development of chaos and chaotic neural networks mainly focuses on their software algorithm improvement [11–18], the hardware implementation of chaos and chaotic neural networks has fallen far behind their software algorithm. Facing with this issue, the research on hardware circuits implementation of chaos and chaotic neural networks becomes increasing important. Chaos has been investigated widely in the last decades and they become increasing interest subjects because of their great potential applications in many fields such as chaotic signal radar [19], secure communications [20–24], chaos-based analog-to-information conversion and image encryption applications [25]. The double-scroll Chua system is the first physical circuit realization of chaos. Since then, other chaotic and hyperchaotic systems with complex chaotic attractors and nonlinear dynamical characteristics have been realized [26–31], and most of them are validated with commercial available discrete electronic components or digital signal processing (DSP) and field programmable gate array (FPGA) [32–42].

Most of the reported and physical implemented chaotic systems are realized using off-the-shelf electronic components with breadboards. The breadboard-based chaotic circuits are suitable for theoretically proving the existence and realizability of chaos, they are non-portable and unstable, and far from the practical application of chaos. Unlike the conventional breadboard-based chaotic circuits, the fully integrated chaotic systems are more stable and convenient than their breadboard-based counterparts. Chaotic systems fully integrated on a single chip should be the development direction of chaotic circuits, and the fully integrated chaotic circuits will greatly enhance the practicality of chaos. For example, two CMOS Chua’s chaotic circuits were reported in Ref. [43], another 2 μm CMOS process integrated chaotic system with high speed operation was introduced Ref. [44], and an integrated multi-scroll chaotic oscillator generating 3- and 5-scroll attractors was reported in Ref. [45].

Because of its simple circuit structure and easy to be theoretically proven, the famous Chen chaotic system [46–50] and its deformation circuits are deeply studied in the past decades. Several realization and implementation of Chen chaotic circuits are presented in Ref. [50], however, these circuits are also realized using commercial available discrete electronic components with breadboards. Based on the existing Chen chaotic circuits and systems, a low voltage low power fully integrated classic Chen chaotic oscillation system is realized in this paper. The post-layout simulation results verified that the fully integrated Chen chaotic oscillation system is feasible and achievable. In addition, the main contributions of this work can be summarized below.1)An operational amplifiers (OA) and an analog multiplier with GlobalFoundries’ 0.18 μm CMOS 1P6M process are designed in this work.2)Unlike the conventional breadboard-based chaotic circuits, a fully integrated Chen chaotic oscillation system using the designed OA and multiplier is presented.3)The fully integrated Chen chaotic system is verified with Cadence IC Tools. The post-layout simulation results demonstrate that the whole power consumption of the fully integrated Chen chaotic system is about 148 mW, its chip area is only 6.15 mm², and the fully integrated Chen chaotic circuit is a more suitable candidate for practical applications.

2. Fully Integrated Chen Chaotic Circuit

The design of fully integrated Chen chaotic circuit is presented in this section. The original Chen chaotic system and its fully integrated circuit is introduced in subsection 2.1, and the implementations of operational amplifier and analog multiplier are introduced in subsection 2.2 and 2.3, respectively.

2.1. Chen Chaotic System

The classic dimensionless state equations of the Chen system can be depicted as follow:where a, b and c are all constants, and a = 35, b = 3, c = 28. When the initial condition is (0, 0, 0), the Matlab numerical simulation results of Chen system are presented in Fig 1, and the chaotic attractors are observed as shown in Fig. 1(a)-(c).

(a)

(b)

(c)

Because the supply voltage of the fully integrated Chen chaotic oscillation system are ±2.5 V, and the output ranges of state variables x, y and z in Fig 1 all exceed ±2.5 V, state variables compression are necessary. After evenly compressed 40 times of the state variables, the state equations of the Chen system could be expressed as:

Let τ = τ_o × t, and τ_o = 10000, and the state equations of the Chen system could be rewritten as:

Based on the existing circuit realizations of Chen chaotic systems, a simplified Chen chaotic oscillation circuit suitable for integration is presented in Fig. 2.

Assuming the gains of the multipliers are all k, and the circuit equation of Fig. 2 could be expressed as:

2.2. Implementation of Operational Amplifier

The designed OA for the integrated Chen chaotic oscillation circuit is shown in Fig. 3. The designed operational amplifier is very simple, and its supply voltages are V_CC = −V_SS = 2.5 V, and it includes two amplification stages and one bias stage.

The transistors M₇-M₁₁ consist of the differential amplification input stage; M₁₃ is the second common source amplification stage, and M₁₂ is the active load of M₁₃; the transistors M₁-M₆ consist of the bias stage of the OA, and the transistor M₁₄ and capacitor C are used for frequency compensation.

The simulated voltage gain and phase frequency characteristics of the OA are shown in Fig. 4. From the mark M₀, we can know that the voltage gain of the OA is about 30dB; From the marks M₀ and M₁, we can calculate that the 3dB bandwidth of the OA is 218.5 kHz; From the marks M₂ and M₃, we can know that the phase margin of the OA is about 86.22°. The power consumption of the OA is about 5.85 mW.

2.3. Implementation of Analog Multiplier

The analog multiplier used in the integrated Chen chaotic oscillation circuit is shown in Fig. 5. The classic Gilbert structure is adopted, M₁ and M₂ consist of the current mirror, and they are the bias stage of the multiplier; M₃ works on its saturation region (also known as amplification region), which can be approximated as a current source to provide bias current for the transconductance stage (M₄ and M₅); M₄ and M₅ consist of the transconductance stage, M₆-M₉ consist of the Gilbert switch stage [51–53], and M₁₀-M₁₃ consist of the load stage of the analog multiplier. The supply voltages of the multiplier are V_CC = −V_SS= 2.5 V, and its power consumption is about 47.7 mW.

The transient response of the designed analog multiplier is presented in Fig. 6. V_i1 and V_i2 are the two input voltages, their input powers are all -10 dBm, and their frequencies are 100 MHz and 10 MHz, respectively. V_out is the output voltage of the analog multiplier. From the above simulation results, it is clear that V_i1 is the high frequency carrier, V_i2 is the low frequency input signal, and the multiplication is realized in the output voltage V_out. From the marks M₀-M₃ in Fig. 6, peak voltages of V_i1 and V_i2 are all about 200 mV, and the peak voltage of V_out is about 4mV. According to V_out = k × V_i1 × V_i2, it is clear that the parameter k in equation (4) is about 0.1.

3. Post-Layout Simulation Results of the Integrated Chen Chaotic Oscillation Circuit

The presented fully integrated Chen chaotic oscillation circuit in Fig. 2 is simulated and verified using Cadence IC Tools with GlobalFoundries’ 0.18 μm CMOS technology. The supply voltages of the fully integrated Chen chaotic circuit are ±2.5 V, and its whole static power consumption is about 148mW. Considering equations (3) and (4), the values of circuit elements are selected as R₁ = R₂ = 2.85 kΩ, R₃ = R₅ = R₆ = R₁₀ = R₁₄ = R₁₆ = R₁₇ = R₁₈ = R₁₉ =10 kΩ, R₄ = R₁₁ = R₁₅ = 200 kΩ, R₈ = R₁₂ = 0.25 kΩ, R₇ = 14.28 kΩ, R₉ = 3.57 kΩ, R₁₃ = 33.33 kΩ, C₁ = C₂ = C₃ = 50 pF.

The chip layout diagram of the Chen Chaotic oscillation system is shown in Fig. 7, and its chip area is 6.15 mm² including all the testing pads.

The Mentor Calibre software is used for circuit verification and parasitic extraction. Based on the layout of the Chen chaotic oscillation circuit in Fig. 7, and connecting the extracted parasitics to the original circuit in Fig. 2, the post-layout simulation results of the integrated Chen chaotic oscillation circuit are presented in Figs. 8 and 9.

(a)

(b)

(c)

Fig. 8 is the transient response of the fully integrated Chen chaotic circuit, and various dynamical oscillations can be observed. From Fig.8, it is clear that the peak amplitudes of output voltages x, y and z are all less than 2 V. Fig. 9 is the phase portraits in x-z, z-y and y-x planes. By comparing Figs. 1 and Fig. 9, a good qualitative agreement between the post-layout chip circuit simulation and numerical simulation is observed.

There are nine operational amplifiers and two multipliers used in the Chen chaotic oscillation circuit. According to the data sheets of operational amplifier LF347 and multiplier AD633JN in Refs. [51–55], the supply voltage of LF347 is ±18 V, and its power consumption is about 500 mW; the the supply voltage of AD633JN is also ±18 V, and its power consumption is also about 500 mW. If the Chen chaotic circuit is realized using commercial available chips LF347 and AD633JN, the whole power consumption is about 5500 mW.

The supply voltage of the fully integrated Chen chaotic oscillation circuit is ±2.5 V, the whole power consumption is about 148 mW, and its chip area is only 6.15 mm². Compared with the conventional realizations using commercial available discrete electronic components with breadboards, the fully integrated Chen chaotic oscillation circuit is a more suitable candidate for practical applications.

4. Conclusion

In this paper, a fully integrated Chen chaotic oscillation system using OAs and multipliers is designed and verified. Unlike the conventional realization using commercial available discrete electronic components with breadboards, the designed Chen chaotic oscillation system is integrated in a single chip. It has the advantages of smaller chip area, lower supply voltage and power consumption. Moreover, it has practical application prospects in demanding portable chaos systems. Besides, it should be further developed from the following objectives to improve the practicability of the fully integrated chaotic circuit. Firstly, other OA and transconductance operational amplifier (OTA) with simpler circuit structures and lower power consumption should be designed to further improve the performance of the fully integrated chaotic circuit. In addition, the realization of integrated chaotic circuits with complex chaotic attractors and nonlinear dynamical characteristics is also considered in our future works.

Data Availability

All data used to support the findings of this study are available from the corresponding author upon request.

Conflicts of Interest

The authors declare that they have no conflicts of interest in this work.

Acknowledgments

This work was supported by the National Natural Science Foundation of China (nos. 61905074 and 61966014), the Natural Science Foundation of Hunan Province (nos. 2020JJ4315 and 2020JJ7065), and the Education Department of Hunan Province Youth Project (nos. 20B216 and 21B0345).

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Copyright © 2022 Ziyi Ouyang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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