About this Journal

IET Computers & Digital Techniques publishes original research and review articles describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test.

The key subject areas of interest are:

• Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation.
• Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance.
• Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues.
• Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware.
• Design for Variability, Power and Aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting.

This journal is published by Hindawi as part of a publishing collaboration with The Institution of Engineering and Technology (IET). It is a fully open access journal produced under the Hindawi and IET brands. 

The IET has a large scale publishing partnership with Wiley, who own Hindawi, and the Wiley IET Hub can be found here.

ISSN: 1751-8601 (Print) 

ISSN: 1751-861X (Online) 

DOI: 10.1049/ietcdt

Content published prior to July 2023 is hosted on the Wiley Online Library and the IET Digital Library. 

IET Computers & Digital Techniques is an open access journal. All articles are immediately available to read and reuse upon publication. More information about our Open Access policy can be found on our copyright page.

Editorial enquiries should be directed to [email protected].

General enquiries should be directed to [email protected].