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International Journal of Antennas and Propagation
Volume 2014 (2014), Article ID 580479, 9 pages
http://dx.doi.org/10.1155/2014/580479
Research Article

Baseband Transceiver Design of a High Definition Radio FM System Using Joint Theoretical Analysis and FPGA Implementation

1Department of Information Management, Tainan University of Technology, Tainan 710, Taiwan
2Department of Finance, Tainan University of Technology, Tainan 710, Taiwan
3Department of Aviation and Communication Electronics, Air Force Institute of Technology, Kaohsiung 820, Taiwan
4Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan

Received 3 January 2014; Accepted 3 March 2014; Published 16 April 2014

Academic Editor: Chung-Liang Chang

Copyright © 2014 Chien-Sheng Chen et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Advances in wireless communications have enabled various technologies for wireless digital communication. In the field of digital radio broadcasting, several specifications have been proposed, such as Eureka-147 and digital radio mondiale (DRM). These systems require a new spectrum assignment, which incurs heavy cost due to the depletion of the available spectrum. Therefore, the in-band on-channel (IBOC) system has been developed to work in the same band with the conventional analog radio and to provide digital broadcasting services. This paper discusses the function and algorithm of the high definition (HD) radio frequency modulation (FM) digital radio broadcasting system. Content includes data format allocation, constellation mapping, orthogonal frequency division multiplexing (OFDM) modulation of the transmitter, timing synchronization, OFDM demodulation, integer and fraction carrier frequency (integer carrier frequency offset (ICFO) and fractional CFO (FCFO)) estimation, and channel estimation of the receiver. When we implement this system to the field programmable gate array (FPGA) based on a hardware platform, both theoretical and practical aspects have been considered to accommodate the available hardware resources.