Analysis of Power Transfer Efficiency of Standard Integrated Circuit Immunity Test Methods

<div>Chip model validation. (a) VDD/VSS port impedance of IC. (b) Package and IC simulation setup. (c) Chip VDD/VSS port impedance <svg height="11.4781pt" id="M30" style="vertical-align:-2.18977pt" version="1.1" viewbox="-0.0498162 -9.28833 36.5317 11.4781" width="36.5317pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M701 633L695 650H264C230 650 223 653 209 675H184C176 622 160 547 140 473L173 471C198 528 219 557 232 573C254 600 272 612 384 612H566L24 18L33 0H597C617 34 651 142 661 179L629 194C598 133 574 92 545 69C510 41 440 40 342 40C274 40 209 42 163 46L701 633Z" id="g50-91"></path><glyph.data ascent="3443" descent="-2856" horiz-adv-x="725" vert-adv-y="725"></glyph.data></g><g transform="matrix(.013,0,0,-0.013,9.048,0)"><path d="M309 -142C211 -61 151 99 151 271S210 601 309 683L288 710C141 611 75 451 75 272V271C75 90 141 -72 288 -169L309 -142Z" id="g50-41"></path><glyph.data ascent="3443" descent="-2856" horiz-adv-x="358" vert-adv-y="358"></glyph.data></g><g transform="matrix(.013,0,0,-0.013,13.702,0)"><path d="M389 0V32C297 38 291 46 291 118V635C234 613 175 595 109 583V556L161 554C203 552 207 547 207 497V118C207 46 201 38 110 32V0H389Z" id="g50-50"></path><glyph.data ascent="3443" descent="-2856" horiz-adv-x="487" vert-adv-y="487"></glyph.data></g><g transform="matrix(.013,0,0,-0.013,20.033,0)"><path d="M98 134C72 134 46 117 46 90C46 73 55 65 60 64C95 55 124 32 124 -4C124 -42 95 -68 44 -89L57 -123C122 -104 194 -60 194 22C194 94 136 134 98 134Z" id="g50-45"></path><glyph.data ascent="3443" descent="-2856" horiz-adv-x="237" vert-adv-y="237"></glyph.data></g><g transform="matrix(.013,0,0,-0.013,25.32,0)"><path d="M389 0V32C297 38 291 46 291 118V635C234 613 175 595 109 583V556L161 554C203 552 207 547 207 497V118C207 46 201 38 110 32V0H389Z" id="g50-50"></path><glyph.data ascent="3443" descent="-2856" horiz-adv-x="487" vert-adv-y="487"></glyph.data></g><g transform="matrix(.013,0,0,-0.013,31.65,0)"><path d="M283 271C283 451 220 610 70 710L48 683C146 603 207 443 207 271S149 -59 48 -142L70 -169C220 -67 283 90 283 271Z" id="g50-42"></path><glyph.data ascent="3443" descent="-2856" horiz-adv-x="358" vert-adv-y="358"></glyph.data></g></svg> comparison.</div>

International Journal of Antennas and Propagation

fig7

Figure 7

Figure 7: Analysis of Power Transfer Efficiency of Standard Integrated Circuit Immunity Test Methods 