Towards Sustainability: Photochemical and Electrochemical Processes Applied for Environmental ProtectionView this Special Issue
Research Article | Open Access
Xianfang Gou, Xiaoyan Li, Shaoliang Wang, Hao Zhuang, Xixi Huang, Likai Jiang, "The Effect of Microcrack Length in Silicon Cells on the Potential Induced Degradation Behavior", International Journal of Photoenergy, vol. 2018, Article ID 4381579, 6 pages, 2018. https://doi.org/10.1155/2018/4381579
The Effect of Microcrack Length in Silicon Cells on the Potential Induced Degradation Behavior
The presence of microcracks may lead to loss in the module output power and safety hazard of the module. This paper investigated whether the existed microscopic microcracks in cells will facilitate the PID behavior. Cells with different degrees of microcracks were fabricated into small modules to undergo the simulated PID test. The I-V performance and EL images of the modules were characterized before and after the PID test. The obtained results demonstrate that with the increase in the microcracked area or length, the modules would show a more serious PID behavior. The mechanism of this microcrack length-related degradation under high negative bias was proposed.
Microcracks refer to the invisible cracks that cannot be easily perceived by the naked eye when a wafer is subjected to mechanical or thermal stress. There are several stages related to the generation of microcracks [1–8]: (i) the cutting process of an ingot or crystal bar due to a local uneven force; (ii) the cell or module fabrication process due to external factors; (iii) improper module installation; and (iv) the power plant operation period due to external factors such as wind or ground subsidence. Since the microcracked silicon wafer is not completely broken apart, microcracks can be detected only through the electroluminescence (EL) test . The presence of microcracks may cause part of the cells to be inactive, leading to the loss in the output power and safety hazard of the module .
In a crystalline silicon cell, current is collected from fingers to the busbar and then through the string connector to the output from the junction box. The generated current of a cell is proportional to the cell active area. The inactive area can be judged by whether the current collection from the finger to the busbar is blocked or not. According to the inactive area of the cell, the number of microcracked cells, and the impact on the output power of modules, microcracks can be divided into three categories: microscopic microcrack, general microcrack, and serious microcrack. Modules with seriously microcracked cells generally need to be replaced in a power station, and those with general microcracks will not affect the power output in the initial stage and will be disposed according to their working condition. Microscopic microcracks generally refer to the microcracks that are single or partial flakes located not at the busbars and basically do not cause failure of the area, and the power degradation of the module with microscopic microcracks should meet the industry standard (i.e., the first-year power degradation less than 2.5%). Therefore, it becomes necessary to develop the means of quantifying the risk of power loss in PV modules with cracked solar cells to ensure their output during the lifetime, and some standards may be discussed and set in the future.
In solar power stations, it is known that modules must be connected in series and parallel to build arrays to meet the load requirements. The connection of single modules in series will produce a high voltage relative to the plane of zero potential (ground). The efficiency of the modules may probably degrade due to this high negative bias under heat and humidity, which is known as the potential induced degradation, PID [10, 11]. A number of factors [12–21], such as stacking faults in the silicon wafer, refractive index of the antireflection coating, resistance of the encapsulant material, and design of the power station, have been found and demonstrated to be related with the PID behavior. However, it has never been investigated whether the existed microscopic microcracks in cells will facilitate the PID behavior of modules.
Herein, we fabricated a series of small modules using solar cells with different microcrack lengths. The small modules were then kept in a climate chamber with constant temperature and humidity for the PID simulation test. The I-V curves and EL images of the small modules were measured before and after the PID test. The obtained results demonstrate that with the increase in the microcrack length, the modules would show a more serious PID behavior. Our work reveals the underlying relationship between the microcrack length in cells and PID of modules.
2. Materials and Methods
Conventional cells with different microcrack lengths were selected via EL and divided into 5 groups with 10 cells each group according to the microcrack length: A (0 cm), B (0–0.9 cm), C (1–2 cm), D (4–5 cm), and E (9–10 cm). The length was measured by the maximum length of the cracked area. Then the cells were fabricated into small modules using the normal process and kept in a climate chamber with constant temperature and humidity for the PID simulation test, after which the I-V and EL of the small modules were measured and analyzed.
3. Results and Discussion
The power loss in crystalline silicon-based photovoltaic modules due to microcracks was investigated by Köntges et al. in 2011 . They analyzed the direct impact of microcracks on the module power and the consequences after artificial aging. The approach of artificial aging they adopt was 200 humidity freeze cycles. The main focus of their research is on the degradation of power due to crack propagation after artificial aging.
Herein, to investigate the effect of microcrack length in silicon cells on the potential induced degradation behavior, in our work, five groups of cells with different degrees of microcracks were fabricated into small modules. After performing the PID test in an environmental test chamber (85°C, 85% RH), the electrical performance was measured using a Pasan tester. The obtained data are listed in Table 1.
As can be seen from Table 1, after the PID test, degradation was observed for the open-circuit voltage (Voc), short-circuit current (Isc), and fill factor (FF). Figure 1 shows the trend of degradation with microcrack length. It can be clearly noted that with the increase in the microcrack length, a larger degradation would occur. The decrease of the parallel resistance (Rsh) is 94.13%, 99.24%, 99.39%, 99.58%, and 99.72% for groups A to E, respectively. These results demonstrate that the longer the microcrack length, the faster the Rsh degrades after the PID test, which increases the probability of providing the shunt for the current, and the trace current Irev2 is greatly improved after the PID test.
From Table 1, it can be also seen that after the PID test, the module efficiency also exhibits a larger degradation with the increase of the microcrack length. The power degradation of module group A without a microcrack is 2.61% after the test, which meets the <5% standard for IEC 62804. Modules of groups B, C, D, and E degraded by 32.02%, 33.80%, 37.53%, and 49.32%, respectively, showing a serious PID phenomenon.
It is shown that with increasing microcrack length, positive charges are easy to gather on the surface of the cell under long-term high bias and high-temperature and humidity conditions. Under the in-built electric field, a large amount of negative charges is attracted to the surface. If a microcrack then exists in the wafer, it can provide a diversion channel for the surface charges, leading to current leakage, which decreases the efficiency of the cell. The larger the microcracked area is, the more leakage occurs, and the greater the efficiency declines.
Figure 2 shows the EL pictures of the cells and small modules before and after the PID test. By comparing these EL pictures, we can find that with the increase in the microcrack length, the EL of the cells after the PID test gradually tarnishes, which is consistent with the degradation trend of modules.
To further verify the obtained results, PIDcon equipment was used to simulate the anti-PID performance of the five sample groups. The parallel resistance change of the samples with test time is shown in Figure 3. It can be seen from the figure that the parallel resistance of sample group A (i.e., without microcrack) first decreased quickly in the initial 12 hours and gradually became steady after that. The Rsh of the B, C, D, and E sample groups decreased rapidly within the initial two hours of the test, especially for group E. After the initial two-hour rapid decrease, it slowly became stable and constant till the end of this test. These results further demonstrate that the increasing microcrack length generally gives a faster decrease rate of parallel resistance after the PID test, indicating a more serious current leakage. Figure 4 shows the PID degradation of modules with different microcrack lengths, and modules are found to degrade less with decreasing microcrack length.
Based on these results, the mechanism of the effect of the wafer microcrack defect on PID is proposed and depicted in Figure 5. The overall crack interface is shown as the dotted area. Figure 5(a) is a scheme of part of the cell, in which the microcrack is located in the cell grid area. The microcrack vertically penetrates through the PN junction. Figure 5(b) is a schematic diagram of the normal crack-free cell. Under light irradiation, photon excites the motion of nonequilibrium carriers in the silicon wafer, and the minorities (i.e., electrons) of the P-type silicon region move to the N-type silicon region. The holes, the minorities of the N-type silicon region, move toward the P-type silicon region and converge through the silver finger to the busbar to generate current. Figure 5(c) is the scheme of charge flow in a microcracked cell. During the lateral or longitudinal movement of electrons and holes, the presence of a microcrack will block the movement of electrons and holes, impeding the transportation of electrons and hence reducing the output current. Due to the limited microcrack area, the degradation in output power is not significant enough to be observed. Figure 5(d) is the scheme of the PID mechanism in a microcracked cell, when the cell is under high temperature/humidity and negative bias; the sodium ions migrate from the glass to the silicon nitride film. Therefore, sodium ions gradually accumulate at the SiNx/Si interface. In the microcrack-free region, the positive charges of sodium ions will attract a large amount of electrons to the silicon surface, which reduces the convergence of electrons to the silver electrodes.
On the other hand, due to the accumulation of negative charges on the silicon surface, the fixed negative charges repel the electrons moving from the P-type silicon side and simultaneously attract the positive charges, thus reducing the number of electrons and holes. In the microcracked region, while the movement of electrons and holes are hindered, sodium ions are impeded when arriving at the silicon nitride layer and the P- and N-microcracked interface regions. Therefore, the sodium ions are easy to gather at the edge of the microcracked region to capture the electrons and become the recombination center for the minorities. When more and more sodium ions accumulate in the microcracked region, the collection of current is largely reduced, leading to current leakage.
This paper focused on the effect of existing microscopic microcracks in cells on the potential induced degradation behavior. Cells with different degrees of microcrack were fabricated into small modules to undergo a simulated PID test. The I-V performance and EL images of the modules were characterized before and after the PID test. The obtained results indicated that with the increase in the microcrack length, the modules would show a more serious PID behavior. The mechanism of this microcrack length-related degradation under high negative bias was proposed.
Conflicts of Interest
The authors declare that there is no conflict of interests regarding the publication of this paper.
This study was financially supported by the research program 13RD1 CECEP (Zhenjiang).
- V. A. Popovich, A. Yunus, M. Janssen, I. M. Richardson, and I. J. Bennett, “Effect of silicon solar cell processing parameters and crystallinity on mechanical strength,” Solar Energy Materials & Solar Cells, vol. 95, no. 1, pp. 97–100, 2011.
- M. Demant, S. Rein, J. Krisch et al., “Detection and analysis of micro-cracks in multicrystalline silicon wafers during solar cell production,” in Proceedings of the 37th IEEE Photovoltaic Specialists Conference, Seattle, 2011.
- J. I. Mölken, U. A. Yusufoğlu, A. Safiei et al., “Impact of micro-cracks on the degradation of solar cell performance based on two-diode model parameters,” Energy Procedia, vol. 27, pp. 167–172, 2012.
- H. Kim, P. Sungeun, B. Kang et al., “Effect of texturing process involving saw-damage etching on crystalline silicon solar cells,” Applied Surface Science, vol. 284, pp. 133–137, 2013.
- I. Berardone, M. Corrado, and M. Paggi, “A generalized electric model for mono and polycrystalline silicon in the presence of cracks and random defects,” Energy Procedia, vol. 55, pp. 22–29, 2014.
- S. S. Ko, C. S. Liu, and Y. C. Lin, “Optical inspection system with tunable exposure unit for micro-crack detection in solar wafers,” Optik- International Journal for Light and Electron Optics, vol. 124, no. 19, pp. 4030–4035, 2013.
- V. T. Dragišić, “Silicon solar wafers: quality control and improving the mechanical properties,” Procedia Engineering, vol. 117, pp. 459–464, 2015.
- K. O. Davis, M. P. Rodgers, G. Scardera et al., “Manufacturing metrology for c-Si module reliability and durability part II: cell manufacturing,” Renewable and Sustainable Energy Reviews, vol. 59, pp. 225–252, 2016.
- M. Köntges, I. Kunze, S. K. Schröder, X. Breitenmoser, and B. Bjørneklett, “The risk of power loss in crystalline silicon based photovoltaic modules due to micro-cracks,” Solar Energy Materials & Solar Cells, vol. 95, no. 4, pp. 1131–1137, 2011.
- S. Pingel, O. Frank, M. Winkler et al., “Potential induced degradation of solar cells and panels,” in Proceedings of the 35th IEEE Photovoltaic Specialists Conference (PVSC), Honolulu, Hawaii, USA, 2010.
- V. Fjallstrom, S. PMP, A. Hultqvist et al., “Potential-induced degradation of thin film solar cells,” IEEE Journal of Photovoltaics, vol. 3, no. 3, pp. 1090–1094, 2013.
- H. Nagel, A. Metz, and K. Wangemann, “Crystalline Si solar cells and modules featuring excellent stability against potential-induced degradation,” in Proceedings of the Eu-Pvsec, Hamburg, Germany, 2011.
- W. Herrmann, M. Schweiger, and G. Mathiak, “Potential-induced degradation – comparison of different test methods and low irradiance performance measurements,” in Proceedings of the 27th European Photovoltaic Solar Energy Conference and Exhibition, Frankfurt, Germany, 2012.
- V. Naumann, D. Lausch, and C. Hagendorf, “Sodium decoration of PID-s crystal defects after corona induced degradation of bare silicon solar cells,” Energy Procedia, vol. 77, pp. 397–401, 2015.
- A. Raykov, H. Hahn, K.-H. Stegemann et al., “Towards a root cause model for the potential-induced degradation in crystalline silicon photovoltaic cells and modules,” in Proceedings of the European Photovoltaic Solar Energy Conference and Exhibition, Paris, France, 2013.
- S. Koch, D. Nieschalk, J. Berghold, S. Wendlandt, S. Krauter, and P. Grunow, “Potential induced degradation effects on crystalline silicon cells with various antireflective coatings,” in Proceedings of the European Photovoltaic Solar Energy Conference and Exhibition, Frankfurt, Germany, 2012.
- K. Mishina, A. Ogishi, K. Ueno et al., “Investigation on anti-reflection coating for high resistance to potential induced degradation,” Japanese Journal of Applied Physics, vol. 53, no. 3S1, article 03CE01, 2014.
- S. Koch, C. Seidel, P. Grunow, S. Krauter, and M. Schoppa, “Polarization effects and tests for crystalline silicon cells,” in Proceedings of the 26th European Photovoltaic Solar Energy Conference and Exhibition, Hamburg, Germany, 2011.
- V. Naumann, D. LAUSCH, A. Hähnel et al., “Explanation of potential-induced degradation of the shunting type by Na decoration of stacking faults in Si solar cells,” Solar Energy Materials & Solar Cells, vol. 120, pp. 383–389, 2014.
- S. Jonai, K. Hara, Y. Tsutsui, H. Nakahama, and A. Masuda, “Relationship between cross-linking conditions of ethylene vinyl acetate and potential induced degradation for crystalline silicon photovoltaic modules,” Japanese Journal of Applied Physics, vol. 54, no. 8S1, article 08KG1, 2015.
- S. Koch, J. Berghold, O. Okoroafor, S. Krauter, and P. Grunow, “Encapsulation influence on the potential induced degradation of crystalline silicon cells with selective emitter structures,” in Proceedings of the European Photovoltaic Solar Energy Conference and Exhibition, Frankfurt, Germany, 2012.
Copyright © 2018 Xianfang Gou et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.