An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="180216.fig.011a" src="https://static.hindawi.com/articles/ijrc/volume-2008/180216/figures/180216.fig.011a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>6-LUT with carry chain</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="180216.fig.011b" src="https://static.hindawi.com/articles/ijrc/volume-2008/180216/figures/180216.fig.011b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>4-LUT with carry chain</td></tr></table></td></tr></table>

<table>Homogeneous LUT structures with carry chain.</table>

International Journal of Reconfigurable Computing

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Figure 11

Figure 11: An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture 